40nm BSI CMOS Image SensorPreview

lectric stack [A1]. Placed after the deposition of the ILD 6-1 (SiCN) and ILD 6-2 (Oxide) layers, this lithographic process provides the mask for the subsequent sequential etches through the oxide and SiCN films [T1]. Unlike standard bond pad opening steps that simply clear passivation from existing top metal surfaces, a cavity photo step specifically defines a structurally recessed trench that provides spatial containment and controlled sidewall spacing for embedded bonding pads [A2]. This geometric confinement is critical for managing mechanical stress during subsequent bonding and packaging processes [P2]. The fundamental mechanism relies on optical lithography to transfer the cavity pattern into a photosensitive resist, subject to the Rayleigh resolution limits dictated by optical diffraction [T1]. The photoresist must possess sufficient thickness and chemical stability to withstand the prolonged, multi-layer plasma etching required to penetrate the thick dielectric stack [A1]. The defined pattern establishes a critical spacing distance between the intended pad edge and the dielectric recess sidewall, which is essential for preventing metal bridging and optimizing interface reliability [A1]. Furthermore, maintaining precise alignment during this step ensures that the resulting cavity accurately overlays the underlying metal interconnects, a fundamental requirement for high-density interconnect applications [P1]. A chemically amplified positive photoresist is typically selected to balance high resolution with the necessary etch resistance (Engineering Practice). The precise patterning of the cavity dictates the final structural integrity of the bonding interface, as geometric gaps heavily influence stress distribution and adhesion [A2]. The interaction between exposure dose and depth of focus directly controls the resist profile, where highly vertical profiles are required to prevent transferring sloped sidewalls into the thick dielectric cavity [A1]. Additionally, the preceding pre-litho cleaning step ensures the ILD surface is free of contaminants, preventing adhesion failure and localized defectivity during the resist development phase [T1]. In 40nm BSI CMOS image sensors, the demand for high interconnect density requires scaled pad geometries without compromising packaging reliability [P1]. The cavity structure mitigates the risks associated with scaling by utilizing the surrounding dielectric as a mechanical buffer [P2]. This layout technique allows underlying active circuitry and multilayer interconnects to remain mechanically isolated from transient packaging loads, successfully balancing die area reduction with structural robustness [P2].