40nm BSI CMOS Image SensorPreview

he upper vertical optical isolation grid [P1]. Unlike the lower or mid vertical grid trench photo steps—which typically define dielectric trenches for subsequent damascene metal filling—this step utilizes a subtractive patterning integration scheme (Engineering Practice). The photoresist pattern formed here directly serves as the soft mask, or defines an intermediate hard mask, for the subsequent anisotropic W and TiN dry etching steps [A2]. By establishing the precise geometric limits of the upper grid, this step ensures optical isolation between adjacent pixels in the back-side illuminated (BSI) architecture, mitigating optical crosstalk and enhancing overall spatial resolution (Engineering Practice). The core mechanism of this step relies on the localized photochemical modification of a resist film to transfer a circuit layout into a physical template [T1]. A chemically amplified photoresist is coated over the wafer, and exposure to deep-ultraviolet (DUV) light triggers a photoacid generator to release acid catalysts [A1]. In positive-tone resists, this acid catalyzes the cleavage of polymer protection groups during a post-exposure bake, rendering the exposed regions highly soluble in an alkaline developer [A1]. The physical resolution limits of this optical transfer are governed by the Rayleigh criterion, expressed as $R = k_1 \frac{\lambda}{NA}$, which dictates that minimizing the exposure wavelength and maximizing the numerical aperture are essential for defining the fine grid structures [T1]. Furthermore, stringent overlay control is achieved using advanced optical alignment sensors that utilize diffraction and phase information from alignment marks to position the wafer with sub-nanometer precision before exposure [P1]. The selection of the photoresist and anti-reflective coating (ARC) stack is driven by the highly reflective nature of the underlying Tungsten and TiN layers [A1]. A multi-layer resist scheme, similar in principle to trilayer stacks utilized in high-resolution patterning, is necessary to suppress standing waves caused by substrate reflections and to improve exposure contrast [P3]. Thick resist applications often suffer from light attenuation with depth, potentially causing inadequate bottom exposure and critical dimension (CD) variations [A1]. Therefore, the resist thickness must be carefully optimized to balance the optical transmittance required for full-depth exposure against the mechanical robustness needed to withstand the subsequent heavy W and TiN plasma etch processes [A1]. Advanced scatterometry metrology is integrated into the workflow to continuously monitor diffracted spectra, allowing for closed-loop control of the lithographic critical dimensions and overlay across the wafer [P1]. At the 40nm technology node, the spatial pitch of the BSI image sensor pixels approaches the optical diffraction limits of standard DUV lithography [P1]. Controlling the exact placement and vertical profile of the photoresist is critical because any profile degradation will transfer directly into the dense Tungsten grid during anisotropic etching, inducing shadowing or asymmetric optical reflections in the final device [T1]. Optical wafer metrology sensors must specifically account for variations in the complex underlying metal stack to maintain signal-to-noise ratios sufficient for tight, process-robust CD control [P1].