40nm BSI CMOS Image SensorPreview

The Silicon Full Trench Etch is a critical step in the nanoscale Backside Illuminated (BSI) CMOS Image Sensor (CIS) flow, designed to form Deep Trench Isolation (DTI) structures [P4]. DTI is physically necessary to block the lateral diffusion of minority carriers, thereby drastically reducing both electrical and optical crosstalk between highly scaled adjacent pixels [P4]. The preceding Oxide Hard Mask Etch provides the robust, highly selective template required to withstand the prolonged and aggressive silicon deep etching chemistry [P3]. Generating a perfectly vertical and smooth trench profile is an absolute prerequisite for the subsequent ashing, cleaning, and SiN fill steps [A1]. Without tight control over the trench morphology, subsequent conformal film depositions will pinch off prematurely, leading to keyhole voids that compromise the isolation integrity of the device [A1]. The fundamental mechanism of this anisotropic etch relies on a time-multiplexed Deep Reactive Ion Etching (DRIE) process based on the Bosch principle [P1]. The process systematically alternates between an isotropic chemical silicon etch and a protective sidewall passivation step [P1]. During the etch phase, SF6 plasma generates highly reactive fluorine radicals that chemically react with the silicon lattice to form volatile SiFx byproducts [P2]. During the passivation phase, the decomposition of gases like C4F8 yields a fluorocarbon polymer that coats the entire trench surface [P1]. Anisotropy is achieved through directional ion bombardment, accelerated by the plasma sheath, which selectively physical-sputters the polymer off the horizontal trench bottom while leaving the vertical sidewall protection intact [P3]. As the trench deepens, radical transport becomes diffusion-limited and ion flux attenuates, necessitating dynamic parameter ramping—such as continuously increasing the bias power—to maintain depassivation efficiency and prevent etch stop [P3]. Material and method selections are driven by the strict requirement to balance etch rate, verticality, and mask selectivity [P1]. A three-step DRIE methodology is frequently selected over the traditional two-step process because it introduces a dedicated 'breakthrough' step [P1]. This decoupling allows the breakthrough step to rely purely on high-energy ion bombardment to remove the bottom polymer, freeing the main etch step to be optimized purely for rapid chemical isotropic etching of the silicon [P1]. Additionally, the cyclic nature of DRIE inevitably produces periodic sidewall undulations known as scallops [P2]. To mitigate this, an in-situ continuous reactive ion etch (RIE) post-treatment utilizing negative bias can be integrated into the tool sequence [A1]. The negative bias enhances the vertical momentum of argon or fluorine ions, shifting the reaction toward physical sputtering to selectively erode the convex peaks of the scallops, thereby smoothing the sidewall [P2]. At the 40nm node for BSI CIS, the physical consequences of the dry etch directly dictate device quantum efficiency and noise performance [P3]. The high-energy ion bombardment physically severs the continuous periodic potential of the silicon crystal, leaving a high density of dangling bonds and disrupted lattice structures at the sidewall surfaces [T2]. These structural defects manifest as interface trap states during subsequent thermal oxidations [P4]. These traps act as highly efficient Shockley-Read-Hall (SRH) recombination centers that capture photogenerated minority carriers, leading to a non-linear degradation of the photodiode's responsivity [P4]. Furthermore, sharp geometric corners or residual scallops exacerbate local electric field crowding, driving up subthreshold conduction limits and exacerbating dark current generation [T1]. Consequently, precise regulation of the plasma physical-chemical balance is strictly required to minimize subsurface damage and prevent white pixel defects in the final sensor array [A2].