40nm BSI CMOS Image SensorPreview

r the Via 5 (V5) pattern from the photoresist into the bulk interlayer dielectric [P4]. Unlike shallow "Pad Oxide Etch" used in front-end-of-line isolation or thin "Oxide Hard Mask Etch" steps, this process requires deep, high-aspect-ratio etching through thick dielectric layers to connect adjacent metal interconnects [A1]. The etch must selectively remove the bulk SiO2 or low-k oxide and land precisely on the underlying ILD 5-1 SiCN etch-stop layer [A1]. This selective termination prepares the wafer for the subsequent SiCN open step and the Metal 6 Trench photolithography in the via-first or dual-damascene sequence [A1]. The fundamental mechanism relies on reactive ion etching (RIE) utilizing a fluorocarbon-based high-density plasma [P1]. In the plasma discharge, neutral radicals dominate the chemical reaction while charged ions are accelerated directionally by the electric field to enhance surface reactions and suppress lateral etching [P4]. Fluorine atoms react with Si–O bonds in the dielectric to form volatile byproducts such as SiFx and COx, which are then pumped out of the chamber [P1]. Simultaneously, fluorocarbon radicals (e.g. (Engineering Practice), CFx) deposit a carbon-rich polymer film on the via sidewalls, significantly reducing the probability of lateral chemical attack by fluorine [P1]. The careful selection of gas composition, such as mixing CF4 or C4F8 with polymerizing agents like CH4, acts to strictly regulate the carbon-to-fluorine (C/F) ratio in the plasma [P1]. Increasing the polymer film formation rate enhances sidewall passivation, which is essential for maintaining vertical via profiles without sacrificing the overall oxide etch rate [P1]. Furthermore, controlling the residence time of the reactive species modulates the competition between radical dissociation and polymer deposition, serving as a core factor for balancing etch rate and selectivity to the underlying mask and stop layers [P1]. At the 40nm node, the physical constraints of aggressive scaling make precise control of the via critical dimension (CD) paramount [T2]. As via diameters shrink, aspect-ratio-dependent etching (ARDE) or RIE lag becomes a severe challenge, where the transport of neutral etchants into narrow features is strictly restricted [P3]. Advanced process control systems and tailored RF bias power are frequently employed to mitigate these transport limitations and ion scattering effects, ensuring uniform via depth across varying local pattern densities and preventing severe interface degradation [P4].