40nm BSI CMOS Image SensorPreview

ration executed immediately following the Light Shield (LS) Backside Contact Ion Implantation (IIP) and directly preceding the LS/Aperture Grid Barrier Deposition (Engineering Practice). During the upstream IIP step, a photoresist mask is utilized to define the implantation regions where energetic dopant ions penetrate the backside silicon [A3]. The high-energy ion bombardment causes the photoresist polymer chains to heavily cross-link, forming a hardened, carbon-rich crust that cannot be removed by simple solvent dissolution (Engineering Practice). The primary objective of this process is to completely eradicate this hardened photoresist and any associated implantation residues to expose a pristine, heavily doped silicon surface [P3]. Unlike other routine post-etch cleaning steps in the flow that primarily target fluorocarbon etch polymers, this specific post-IIP clean must address thick, ion-hardened organics while preserving the ultra-shallow doped layer required for the subsequent formation of a low-resistance ohmic contact [T1]. If these organic residues and native oxides are not meticulously removed, they will physically obstruct the interfacial connection between the silicon and the upcoming barrier metal, fundamentally disrupting the metal-semiconductor contact physics [T1]. The physical and chemical mechanism of this step relies on a sequential "oxidize-and-remove" strategy, typically combining an oxygen-based plasma ashing phase with targeted wet chemical etching [P3]. Initially, the wafer is exposed to an O2 plasma asher, where reactive oxygen species chemically oxidize the carbon-based photoresist into volatile compounds such as carbon monoxide and carbon dioxide [P3]. This plasma interaction simultaneously reacts with the exposed silicon substrate, generating a very thin, chemically altered silicon dioxide layer that encapsulates near-surface crystalline damage and trapped contaminants [P3]. Following the plasma phase, the substrate is immersed in a dilute hydrofluoric acid (HF) wet bath [P4]. The HF selectively dissolves this sacrificial plasma-grown oxide layer and sweeps away chemically adsorbed impurities, achieving a highly controlled, quantitative consumption of the damaged silicon surface [P3]. Finally, an alkaline oxidizing formulation, such as an ammonia-peroxide mixture (APM), is often employed to remove particulate contamination and further strip trace residues through mild chemical etching [P3]. The selection of this combined dry-wet methodology is dictated by the chemical resilience of the upstream residues and the extreme surface sensitivity of ohmic contacts [A2]. A purely wet strip is chemically insufficient for breaking down ion-implanted resist crusts, whereas relying solely on plasma ashing leaves behind a damaged, non-stoichiometric surface layer that severely degrades silicide or barrier metal growth quality [P3]. By integrating O2 plasma with sequential HF and APM cleans, the process precisely confines silicon removal to the nanometer scale while maintaining high selectivity to surrounding isolation dielectrics [P3]. The interaction of control parameters is delicate: the asher's plasma power and thermal settings must be high enough to volatilize the cross-linked organics but kept below the threshold that would drive dopants deeper into the substrate or cause excessive thermal oxidation [P3]. Simultaneously, the concentration and immersion time of the wet chemical baths dictate the total silicon loss, which directly impacts the final sheet resistance and specific contact resistivity [P3]. For a 40nm BSI CMOS Image Sensor, the constraints on this step are exceptionally stringent due to the ultra-shallow nature of the backside contact junctions (Engineering Practice). At advanced nodes, the thermal budget is strictly limited, meaning the implanted dopants are often activated at lower temperatures and reside within a very narrow depth profile near the surface [P3]. Excessive silicon consumption during the HF or APM wet cleans would physically etch away the region of peak dopant concentration [P3]. According to semiconductor physics, a reduction in the surface carrier concentration drastically widens the depletion region at the metal-semiconductor interface, exponentially reducing the probability of quantum mechanical tunneling and thereby destroying the ohmic nature of the contact [T1]. Therefore, the chemical etch rates must be tightly controlled to remove only the damaged atomic layers without depleting the active carrier profile [P3].