40nm BSI CMOS Image SensorPreview

Backside Substrate Contact - Photo

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BPMD Etch

HKD/AR2 Etch
310Pre Litho Cleaning311Backside Substrate Contact - Photo312BPMD Etch313HKD/AR2 Etch314HKD/AR1 Etch315RIE etch, Si Back etch316LS Backside Contact Ion Implantation317Ashing & Strip/Clean

Process Cross-Section

ISP WaferCIS Wafer · BacksideSBST_CONT · BPMD Etch (SiO)PRBPMDTaOAlOP+ implanted regionSiCESLSiO2CuTaAlSiN

Step highlight

BPMD etch creates a vertical pathway through thick isolation dielectric to enable subsequent high-k dielectric and anti-reflective layer removal .

In depth

Following the backside photolithography step, the BPMD (Backside Pre-Metal Dielectric) Etch transfers the substrate contact pattern into the previousl

y deposited SiO layer . This step creates the initial vertical pathway through the thick isolation dielectric, preparing the structure for subsequent high-k dielectric (HKD) and anti-reflective (AR) layer removal . Unlike standard front-side PMD etches, this specific backside process must align precisely with the underlying silicon grid and isolation structures without degrading the thinned substrate's mechanical or electrical integrity . Ultimately, opening this contact window enables the subsequent formation of a low-resistance metal-semiconductor interface that defines the device's backside reference potential . The etching of the SiO-based BPMD layer is primarily driven by anisotropic reactive ion etching (RIE) . In a typical fluorocarbon-based plasma, the chemical radicals react with the silicon dioxide to form volatile byproducts, while the vertical ion bombardment provides the directionality needed to carve out high-aspect-ratio profiles . During the etch, a carefully balanced polymer layer deposits on the sidewalls of the etched PMD stack, which suppresses lateral undercutting and maintains strict critical dimension (CD) control . This mechanism is essentially a kinetic competition between isotropic chemical etching and anisotropic physical sputtering . By manipulating the plasma density and substrate bias voltage, process engineers ensure that the vertical etch rate dominates, allowing the contact hole to reach the underlying AR1/AR2 layers with a highly vertical profile . Anisotropic dry etching is selected over wet chemical etching because wet methods, while capable of excellent atomic-layer selectivity, suffer from isotropic profiles that would fatally widen the contact critical dimensions . Fluorocarbon gas ratios and chamber pressure interact directly to dictate the etch selectivity between the BPMD SiO layer and the underlying dielectric etch-stop layers . Increasing the polymerizing gas ratio thickens the protective sidewall passivation but can lead to a complete etch stop at the bottom of deep features due to polymer accumulation (Engineering Practice). Conversely, increasing the ion energy enhances the removal of these passivating layers at the trench bottom, ensuring continuous etching but risking punch-through of the underlying stop layer . Therefore, the etch recipe must strictly balance physical bombardment and chemical passivation to achieve precise nanometer-scale thickness controllability . At the 40nm node for BSI image sensors, the aggressive downscaling of pixel pitch requires highly confined substrate contacts to maximize the active photodiode area (Engineering Practice). As device dimensions shrink, the structures become increasingly susceptible to thermodynamic limits and alignment offsets . This makes the BPMD etch extremely challenging, as the contact must be perfectly centered between isolation structures to avoid inducing catastrophic junction leakage currents . Furthermore, maintaining high-aspect-ratio contact integrity is critical to ensuring proper eventual metal fill and minimizing contact resistance, which remains heavily dependent on the available effective overlap area .

Risks & Challenges

  • [High] RIE Lag and Incomplete Etch: Excessive polymer deposition at the bottom of the high-aspect-ratio contact hole can prematurely halt the etching process . If the ion bombardment energy is insufficient to continuously clear the fluorocarbon passivation, the BPMD will not be fully removed, preventing proper electrical connections .
  • [Medium] Loss of Critical Dimension (Bowing/Undercut): Insufficient polymer pre-deposition on the sidewalls of the etched PMD allows lateral chemical etching to widen the contact hole . This isotropic lateral etching can lead to electrical shorts with adjacent backside structures as contact pitches are aggressively scaled .
  • [Medium] Etch Punch-Through: High ion energy or poor etch selectivity causes the plasma to break through the underlying dielectric etch-stop layers . This can expose the thinned silicon substrate prematurely to plasma damage, altering the local energy band profile and degrading device performance .
  • [Low] High Contact Resistance due to Misalignment: Photolithography alignment offsets during the preceding step can force the BPMD etch to land partially on isolation structures rather than the target active area . This reduces the effective overlap area between the subsequent contact metal and the underlying silicon, which significantly increases the metal-semiconductor contact resistance .

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Related steps

  • Pre Litho Cleaning
  • Backside Substrate Contact - Photo
  • HKD/AR2 Etch
  • HKD/AR1 Etch
  • RIE etch, Si Back etch
  • LS Backside Contact Ion Implantation