HKD/AR1 Etch - 40nm BSI CMOS Image Sensor 40nm

the specific gas mixture ratio dictates the polymer deposition rate on the sidewalls, which acts as a protective passivation layer to prevent lateral undercutting and notch formation during the etch progression .

In the 40nm BSI CMOS Image Sensor flow, the backside substrate contact (SBST_CONT) i

s essential for providing a stable electrical bias to the thinned silicon substrate, which defines the depletion region and prevents pixel blooming . Following the photoresist patterning and initial BPMD/AR2 etching, the HKD/AR1 Etch step is responsible for breaking through the remaining high-k dielectric (HKD) and anti-reflective (AR1) passivation layers to prepare the underlying structure for further processing . This step serves as the critical breakthrough etch before the subsequent reactive ion etching (RIE) of the bulk silicon and the ensuing ion implantation processes that will ultimately dictate the metal-semiconductor contact barrier . Precise removal of these specific dielectric layers without inducing severe micro-masking or catastrophic profile deformation is critical for the mechanical and electrical integrity of the final backside contact . The HKD/AR1 etching relies fundamentally on an ion-assisted plasma etching mechanism, where directionally accelerated ions and neutral reactive radicals work synergistically . Because high-k dielectrics often possess extremely strong atomic bonds and high bond energies, purely chemical removal using neutral radicals is highly inefficient and tends to be isotropic . Consequently, the process utilizes radio-frequency (RF) power to accelerate charged ions across the plasma sheath, providing the kinetic energy necessary to physically break surface bonds and lower the chemical reaction activation energy . This energetic ion bombardment promotes the formation of volatile etch products while simultaneously suppressing lateral etching, thereby maintaining a highly anisotropic and vertical contact profile . The balance between chemical etching and physical sputtering must be tightly controlled to prevent plasma-induced damage, such as charge-up phenomena or lattice displacement in the underlying silicon, which could otherwise degrade the electrical properties of the junction . A tailored fluorocarbon-based or specialized halogen plasma chemistry is typically selected to achieve the necessary etch selectivity between the dense AR1/HKD stack and the surrounding protective masking materials . The RF power and bias voltage are the primary tuning parameters; insufficient ion energy fails to overcome the bond strength of the high-k material, whereas excessive energy exacerbates mask erosion and introduces severe lattice damage to the target substrate . Furthermore, the specific gas mixture ratio dictates the polymer deposition rate on the sidewalls, which acts as a protective passivation layer to prevent lateral undercutting and notch formation during the etch progression . This delicate parameter interplay ensures that the contact hole maintains its critical dimension (CD) and verticality before transitioning to the pure silicon back etch phase .

[High] Incomplete Dielectric Etch (Under-etch): If the applied ion energy or plasma flux is insufficient to break the strong covalent bonds of the high-k layer, residual dielectric material will remain at the bottom of the contact hole . This unetched insulating layer physically blocks the subsequent processing steps, preventing proper electrical connection during metallization and leading to an open circuit or severely elevated contact resistance .
[Medium] Plasma-Induced Lattice Damage: Excessive RF bias voltage accelerates ions to excessive kinetic energies, which can implant structural defects or create deep-level traps in the exposed semiconductor substrate upon clearing the dielectric . This physical damage alters the local density of states and can degrade the eventual metal-semiconductor contact properties or cause localized subthreshold leakage .
[Medium] RIE-Lag and CD Variation: In small critical-dimension features, the restricted transport of active radicals and ions to the trench bottom can lead to RIE-lag, causing non-uniform etch depths across the wafer . This localized aspect-ratio-dependent etching compromises the process window for the subsequent silicon back etch and contact implant steps, leading to variable contact resistance across the sensor array .
[Low] Sidewall Notching or Undercutting: Imbalances in the etching-to-passivation gas ratio can result in insufficient polymer deposition, leaving the dielectric sidewalls vulnerable to lateral attack by neutral radicals . This localized isotropic etching creates structural notches that can trap subsequent liner or metal layers, leading to poor step coverage, void formation, or long-term reliability failures .

In the 40nm BSI CMOS Image Sensor flow, the backside substrate contact (SBST_CONT) i

[High] Incomplete Dielectric Etch (Under-etch): If the applied ion energy or plasma flux is insufficient to break the strong covalent bonds of the high-k layer, residual dielectric material will remain at the bottom of the contact hole . This unetched insulating layer physically blocks the subsequent processing steps, preventing proper electrical connection during metallization and leading to an open circuit or severely elevated contact resistance .
[Medium] Plasma-Induced Lattice Damage: Excessive RF bias voltage accelerates ions to excessive kinetic energies, which can implant structural defects or create deep-level traps in the exposed semiconductor substrate upon clearing the dielectric . This physical damage alters the local density of states and can degrade the eventual metal-semiconductor contact properties or cause localized subthreshold leakage .
[Medium] RIE-Lag and CD Variation: In small critical-dimension features, the restricted transport of active radicals and ions to the trench bottom can lead to RIE-lag, causing non-uniform etch depths across the wafer . This localized aspect-ratio-dependent etching compromises the process window for the subsequent silicon back etch and contact implant steps, leading to variable contact resistance across the sensor array .
[Low] Sidewall Notching or Undercutting: Imbalances in the etching-to-passivation gas ratio can result in insufficient polymer deposition, leaving the dielectric sidewalls vulnerable to lateral attack by neutral radicals . This localized isotropic etching creates structural notches that can trap subsequent liner or metal layers, leading to poor step coverage, void formation, or long-term reliability failures .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges