40nm BSI CMOS Image SensorPreview

owing the deposition of the BPMD SiO layer and the underlying HKD/AR2 TaO and HKD/AR1 AlO layers [A1]. Unlike previous pre-litho cleans (such as steps #7, #13, #27, #49, and #73) which prepare front-side active area, gate, or interconnect layers, this distinct step conditions the backside passivation dielectric for deep contact photolithography [A1]. The primary function of this step is to render the SiO surface completely free of organic and inorganic impurities before the photoresist and bottom anti-reflective coatings are applied [A1]. Thorough cleaning procedures are essential to prevent contamination of the process equipment and to assure reliable downstream fabrication results [P4]. Preparing a pristine surface is critical because any structural defects transferred during the subsequent contact etch will directly impact the specific contact resistance and interfacial properties of the final backside contact [T1]. The physical and chemical mechanisms of this wet cleaning process rely on the gentle removal of particulate and organic matter without chemically attacking the deposited BPMD SiO layer [A3]. Atomically smooth surfaces are generally targeted after surface treatments, as any induced surface roughness can degrade subsequent lithographic depth-of-focus and patterning fidelity [P2]. The cleaning agents utilize specific chemical interactions to detach particles via zeta potential modulation and oxidize trace organics without causing structural degradation [A3]. It is crucial that this pre-litho cleaning step does not alter the underlying dielectric's stoichiometry or generate unwanted interfacial trap states ($D_{it}$), which could perturb the local electrical field or degrade the eventual ohmic contact properties [T1]. The selection of the cleaning chemistry must balance high particle removal efficiency with strict material compatibility [A3]. Aggressive cleaning formulations can inadvertently damage dielectric materials or absorb into them, which negatively alters their dielectric constant and physical integrity [A2]. Therefore, mild, highly selective aqueous chemistries are employed to eliminate contaminants while leaving the BPMD SiO surface completely intact [A3]. Furthermore, proper surface conditioning during this step establishes the appropriate surface free energy required to prevent coat-out defects and ensure uniform coating of the photoresist in the immediate next step [P1]. At the 40nm BSI (Backside Illumination) node, the backside substrate contact requires precise etching through a thick, multi-layer dielectric stack consisting of SiO, TaO, and AlO [P4]. The pre-litho clean must ensure absolutely zero defectivity on the initial SiO surface; otherwise, residual nanoscale particles will act as micromasks, leading to incomplete etching of the high-k/anti-reflective layers and causing open contacts [A1].