40nm BSI CMOS Image SensorPreview

SiN Strip

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Blanket B Well Implant

Ox growth
25SiN Hard Mask Deposition26SiO Hard Mask Deposition27Pre Litho Cleaning28Shallow Trench Isolation - Photo29Oxide Etch30Nitride Etch31Si Etch32Ashing & Strip/Clean33Trench Sidewall Passivation34STI Liner Oxidation35STI Fill Conformal CVD Liner36STI Fill Liner Etchback37Oxidation Preaclean38STI Fill Conformal CVD Oxide39STI Fill Post Clean40STI Conformal CVD Anneal41Pre-CMP Oxide Deposition42STI CMP43STI CMP Post Cleaning44STI Final Densification Anneal45Wet Deglaze Etch46SiN Strip47Blanket B Well Implant

Process Cross-Section

STI · S23 · Blanket B Well Implant (P-well Final)Blanket B implant (11B+)SiO2 liner (SACVD)SiO2 (SACVD bulk fill)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)SiNSiP-well (implanted region)

Step highlight

The Blanket Boron (B) Well Implant is executed immediately following the removal of the STI silicon nitride mask to establish the baseline p-type conductivity across the semiconductor substrate .

In depth

The Blanket Boron (B) Well Implant is executed immediately following the removal of the STI silicon n

itride mask to establish the baseline p-type conductivity across the semiconductor substrate . By performing this step as a blanket implant without a photoresist mask, the process completely avoids the lateral ion scattering and proximity effects typically associated with high-energy masked implants . This foundational doping layer serves to isolate adjacent active regions, prevent subsurface punch-through between deeply scaled devices, and define the electrical environment for subsequent localized N-well and channel engineering . Integrating this step directly after STI completion ensures that the deep p-well profile is securely positioned relative to the isolation trenches, preparing the bare substrate for the subsequent protective well oxide growth step . The physical mechanism of this step relies on the high-energy acceleration of boron ions into the silicon crystal lattice to modulate its bulk electrical conductivity . As the boron ions penetrate the substrate, they lose kinetic energy through two primary mechanisms: inelastic collisions with target electrons (electronic stopping) at higher energies, and elastic collisions with target nuclei (nuclear stopping) as the ions decelerate . By precisely tuning the implantation energy, process engineers can place the projected range deep within the substrate, deliberately creating a retrograde well profile . This retrograde profile features a lower dopant concentration near the surface to maximize carrier mobility and control threshold voltage, while maintaining a heavily doped deep region to suppress parasitic bipolar action and prevent circuit latchup . Furthermore, this deep, highly doped region effectively prevents depletion layer punch-through between adjacent source and drain regions in deeply scaled transistors . Boron is selected as the dopant species because it introduces acceptor energy levels near the valence band, allowing for the efficient thermal excitation of holes at room temperature . The implantation energy and dose serve as the critical control parameters; higher energy dictates a deeper projected range according to standard range-energy physics, while the dose determines the total integrated carrier concentration . Because this is a blanket implant, the process intrinsically avoids the threshold voltage shifts and device mismatch issues that arise when scattered ions emerge from the edges of thick photoresist masks and inadvertently dope adjacent channel regions . However, the initial boron distribution must be carefully calibrated to account for transient enhanced diffusion and dopant segregation during subsequent thermal steps . Specifically, boron exhibits a strong thermodynamic tendency to segregate into adjacent shallow trench isolation (STI) oxides during later thermal cycles, an effect that can deplete the silicon active edge and induce severe perimeter junction leakage . In a nanoscale Backside Illuminated (BSI) CMOS Image Sensor architecture, the blanket p-well plays a dual role in both logic transistor performance and pixel array isolation . The deep, continuous p-type layer creates a built-in vertical potential gradient that assists in driving photo-generated electrons toward the n-type collection regions of the photodiodes, thereby minimizing electrical crosstalk between adjacent pixels . Additionally, the continuous blanket approach ensures uniform substrate bias continuity across the expansive pixel array, which is critical for minimizing localized dark current variations and maintaining high signal-to-noise ratios in advanced imaging nodes .

Risks & Challenges

  • [High] Boron Segregation and Perimeter Leakage: During subsequent thermal cycles, boron dopants have a strong tendency to segregate along the boundaries of the STI sidewall oxide . This localized dopant depletion at the active area edges alters the metallurgical junction profile, leading to locally enhanced electric fields and elevated perimeter diode leakage current .
  • [Medium] Retrograde Profile Smearing: The electrical effectiveness of the retrograde well relies on maintaining a sharp concentration gradient between the heavily doped deep region and the lightly doped surface . Excessive thermal budgets in downstream steps can drive boron diffusion toward the surface, which inadvertently raises transistor threshold voltages and degrades surface carrier mobility .
  • [Medium] Unannealed Implantation Damage: The nuclear stopping mechanism during boron deceleration causes elastic collisions that displace silicon atoms from their lattice sites, generating point defects and structural damage . If subsequent thermal processing is insufficient to fully repair this lattice damage, the residual structural defects will act as generation-recombination centers that significantly increase localized dark current .
  • [Low] Projected Range (Rp) Variation: Fluctuations in the ion implanter's accelerating voltage directly alter the kinetic energy of the incoming boron ions, shifting their final depth distribution within the substrate . An abnormally shallow projected range fails to provide adequate deep punch-through protection, while concurrently increasing surface impurity scattering and reducing transistor drive current .

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Related steps

  • SiN Hard Mask Deposition
  • SiO Hard Mask Deposition
  • Pre Litho Cleaning
  • Shallow Trench Isolation - Photo
  • Oxide Etch
  • Nitride Etch