The etch process is inherently limited by the diffusion of active reactant species through the newly formed salt layer .
In depth
The STI Fill Liner Etchback step plays a critical role in advanced device integration by reshaping the geometry of previously deposited dielectric layers . Prior to this st
ep, a conformal CVD oxide liner is deposited over the trench, which often narrows the trench opening and creates nearly vertical or re-entrant sidewall profiles . The etchback process selectively removes a portion of this conformal liner to widen the top of the trench opening, modifying the sidewall slope to be more tapered . This structural modification is essential to prevent premature pinch-off and void formation during the subsequent bulk CVD oxide gap-fill step . Unlike the preceding liner deposition, which uniformly coats the trench, this etchback step actively subtracts material to tailor the geometric profile for optimal downstream gap-fill integration . The physical mechanism of this step relies on highly selective, low-damage chemical etching, typically utilizing a downstream plasma containing NH3 and NF3 gases . Neutral active species generated in the remote plasma diffuse into the trench and react with the SiO2 liner to form a volatile or sublimable intermediate product, such as ammonium fluorosilicate salt ((NH4)2SiF6) . This reaction fundamentally differs from physical ion bombardment, as it uses solid-gas phase transformation principles to achieve material removal without damaging the underlying silicon lattice . The etch process is inherently limited by the diffusion of active reactant species through the newly formed salt layer . Consequently, the etch rate slows down over time, exhibiting a self-limiting behavior that provides precise control over the etched depth and the final profile of the trench . A subsequent gentle heating step sublimates this salt layer, leaving a clean, reshaped oxide surface behind . The selection of a downstream chemical dry etch over conventional reactive ion etching (RIE) is driven by the need to eliminate ion-induced damage and strictly control the etch amount on a nanometer scale . The primary control parameters are the NF3 to NH3 gas ratio, plasma exposure time, and sublimation temperature . Adjusting these parameters governs the reaction kinetics and the spatial distribution of the salt formation, directly impacting the final sidewall slope and the dimension of the liner opening . Because the fluorine atoms react rapidly to form the required intermediate compounds, the process effectively restructures the trench boundaries . However, managing the process requires careful optimization to avoid complete removal of the liner at the trench bottom, which must be preserved to buffer mechanical stress and prevent lattice defects in the active area . For 40nm BSI CMOS Image Sensors, ensuring pristine pixel isolation is paramount to minimizing dark current and electrical crosstalk between adjacent photodiodes . At this deep sub-micron scaling, the trench aspect ratio is high enough that standard sub-atmospheric CVD (SACVD) or high-density plasma (HDP) processes fail to provide void-free filling without profile engineering . Introducing this Liner-Etch-Gap-fill (L-E-G) sequence allows manufacturers to improve the trench sidewall slope dynamically, artificially lowering the effective aspect ratio presented to the final gap-fill step . This enables the successful integration of reliable isolation structures without requiring the adoption of entirely new, fundamentally unproven gap-fill dielectrics .
Risks & Challenges
[High] Gap-fill Voids due to Insufficient Etchback: If the etchback time is too short or the reactant concentration is insufficient, the top opening of the conformal liner will not be widened adequately . This leads to early sealing of the trench during the subsequent gap-fill step, creating trapped voids that severely degrade the electrical isolation performance of the structure .
[Medium] Active Silicon Damage from Over-etching: If the self-limiting chemical reaction is poorly controlled and etches too much oxide, the underlying silicon at the trench corners can be exposed . Subsequent processing on this bare silicon can lead to stress concentration and localized electric field enhancement, which directly increases parasitic subthreshold leakage current .
[Medium] Etch Non-uniformity from Pattern Loading: The chemical etch-back process is highly sensitive to the local SiO2 open area, leading to significant loading effects across the wafer . On patterned wafers containing both dense pixel arrays and isolated logic areas, this causes varying etch depths, reducing overall process uniformity and constraining the viable process window .
[Low] Residual Fluorine Contamination: If the post-etch sublimation step is incomplete, residual fluorine from the ammonium salt layer can remain trapped within the trench . During subsequent high-temperature operations, this fluorine can outgas and inadvertently react with the surrounding silicon dioxide or silicon, leading to unintended etching and degraded reproducibility .