an optimized oxide surface provides a suitable energy state and chemical termination for the adhesion of subsequent anti-reflective coatings and photoresist layers used in the STI lithography module .
In depth
The SiO Hard Mask Deposition step serves as a critical pattern transfer layer within the Shallo
w Trench Isolation (STI) module for the 40nm BSI CMOS Image Sensor . Positioned immediately after the SiN Hard Mask Deposition, this silicon oxide layer completes a composite hard mask stack required for high-fidelity trench definition . As device dimensions shrink to the nanoscale, photoresist alone lacks the physical etch resistance necessary to mask deep or high-aspect-ratio trench etching, necessitating an intermediate sacrificial layer . This specific SiO layer is distinct from earlier Deep Trench Isolation (DTI) hard masks because it is specifically engineered to pattern the underlying SiN and substrate for shallow, dense active region isolation, rather than for deep, high-aspect-ratio pixel boundary isolation . Following this deposition, the wafer proceeds to lithography and oxide etching, where this SiO film will precisely transfer the patterned photoresist design into the robust SiN layer below . The deposition of the silicon oxide hard mask typically relies on Chemical Vapor Deposition (CVD) techniques, where precursor gases react near or on the heated wafer surface to form a solid dielectric film . The chemical reaction kinetics involve the adsorption of silicon-containing precursors and oxidizing agents onto the substrate, followed by surface migration and by-product desorption . The resulting film's density and mechanical stress are directly determined by the deposition temperature, plasma power, and gas ratios . Managing the intrinsic stress of this deposited film is crucial, as mismatched thermal expansion coefficients between the deposited oxide, the underlying silicon nitride, and the silicon substrate can induce structural bending or localized defects . Viscoelastic models demonstrate that structural rearrangement during or after deposition generates mechanical forces that must be carefully tuned to prevent substrate damage and mobility degradation . Silicon oxide is selected as the top hard mask material primarily for its exceptional etch selectivity against both the overlying photoresist and the underlying silicon nitride layer . During the subsequent anisotropic reactive ion etching (RIE) step, the varying material removal rates between the polymer-based resist, the SiO layer, and the SiN layer allow for precise dimensional control without premature mask erosion . The deposition parameters, such as precursor flow rates and RF power, are optimized to balance the deposition rate with film conformality and density . A denser oxide provides superior etch resistance but may increase compressive stress, which can inadvertently affect carrier mobility in nearby active regions through thermal-mechanical-structural coupling . Furthermore, an optimized oxide surface provides a suitable energy state and chemical termination for the adhesion of subsequent anti-reflective coatings and photoresist layers used in the STI lithography module . In a 40nm BSI CMOS Image Sensor architecture, the active area pitch is highly aggressive, demanding near-perfect pattern fidelity to minimize electrical crosstalk and edge leakage . At these nanometer dimensions, any line edge roughness or critical dimension (CD) loss during the initial hard mask open can translate into asymmetric trench profiles, which subsequently concentrate electric fields at the trench corners and cause detrimental transistor double-peak phenomena . The use of a composite SiO/SiN mask mitigates these risks by allowing the top SiO layer to be etched with highly selective fluorocarbon chemistries, creating a vertical and robust template for the deeper SiN and silicon etches .
Risks & Challenges
[High] Hard Mask Delamination: Driven by extreme intrinsic stress gradients between the newly deposited SiO layer and the underlying SiN film, which can exceed the interfacial adhesion forces . This thermal-mechanical mismatch causes the film to peel or crack, leading to catastrophic pattern transfer failure during subsequent etching (Engineering Practice).
[Medium] Insufficient Etch Resistance: Caused by incomplete precursor dissociation or low deposition temperatures, resulting in a porous oxide network with low physical density . A porous SiO mask will be eroded too rapidly during the subsequent reactive ion etching, causing critical dimension (CD) loss and exposing the underlying SiN prematurely .
[Medium] Particle Generation and Pinholes: Occurs when gas-phase nucleation happens due to unoptimized precursor flow ratios or chamber pressure, leading to the formation of macro-particles that land on the wafer surface . These particles create micro-masking effects or pinholes in the hard mask, which ultimately transfer down into the substrate during trench etching, causing localized electrical isolation failures .