40nm BSI CMOS Image SensorPreview

STI) regions and define the boundaries of the transistors [T1]. Following photolithography, the "Oxide Etch" step transfers the resist pattern into the underlying deposited SiO hard mask [P1]. This thick oxide layer is required because the photoresist alone cannot withstand the prolonged plasma exposure needed for the subsequent deep silicon trench etch [P2]. By opening the oxide hard mask first, the sequence prepares a robust, highly selective template for the subsequent nitride and silicon etching steps [A2]. Unlike pad oxide etch steps that remove thin stress-relief layers, or PMD etch steps that form deep contact vias, this step exclusively defines the primary structural boundaries of the active regions by accurately transferring the lithographic pattern into a thick sacrificial masking layer [A1]. The pattern transfer is driven by reactive ion etching (RIE), which couples physical sputtering with chemical reactions to achieve high anisotropy [P2]. The etching typically employs fluorocarbon-based plasmas (such as CF4 or CHF3 mixed with Ar) to selectively remove SiO2 [P2]. In the low-pressure plasma discharge, high-energy ions accelerate across the plasma sheath to bombard the surface, breaking strong Si-O bonds and providing the activation energy required for etching [P2]. Simultaneously, neutral fluorocarbon radicals adsorb onto the activated surface and react with the oxide to form volatile byproducts like SiF4 and CO or CO2, which are subsequently pumped away (Engineering Practice). The balance between the polymerizing nature of the fluorocarbon radicals and the vertical ion bombardment ensures that horizontal surfaces are etched rapidly while vertical sidewalls are protected by a thin fluoropolymer layer, thereby maintaining a highly vertical hard mask profile [P2]. The selection of a fluorocarbon-based dry etch is dictated by the need for vertical profiles and high chemical selectivity to the underlying silicon nitride layer [P2]. A higher carbon-to-fluorine ratio in the feed gas enhances polymerization on the underlying nitride, abruptly halting the etch process once the oxide is completely cleared [P1]. Modulating the bias power directly controls the ion bombardment energy, which dictates the physical removal of the protective polymer at the trench bottom [P2]. If the ion energy is too low, excessive polymer deposition can lead to etch stop; conversely, if the energy is too high, the selectivity to the photoresist is degraded, causing resist faceting and critical dimension (CD) loss (Engineering Practice). For a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, precise dimensional control of the active area is critical to maximizing the pixel fill factor and minimizing dark current [P3]. Any micro-masking or CD bias introduced during this oxide hard mask open will be amplified during the subsequent deep silicon etch, directly impacting the final trench geometry and increasing the risk of voids during subsequent gap-fill processes [P1]. Furthermore, achieving a strict vertical profile in the oxide mask minimizes line-edge roughness, which is essential to prevent localized stress concentrations that could degrade carrier mobility or induce subthreshold leakage in the final scaled devices [T3].