40nm BSI CMOS Image SensorPreview

hing and cleaning, serving as the critical interface preparation before subsequent CVD dielectric fill [T1]. In the 40nm CMOS Image Sensor (CIS) process flow, this step repairs plasma-induced lattice damage on the trench sidewalls and bottoms generated during the preceding reactive ion etch phase [A2]. Furthermore, growing this thin thermal oxide provides a pristine silicon-dielectric interface that minimizes interface trap states, which are a primary source of dark current in advanced image sensors [P1]. The nitride hardmask present on the active area top surface prevents oxidation in those regions, restricting oxide growth strictly to the trench interior [T1]. The fundamental mechanism of this step relies on high-temperature thermal oxidation kinetics, where oxygen diffuses into the silicon lattice to consume surface silicon and form silicon dioxide [T1]. A critical physical outcome of this process is trench corner rounding, which occurs because the three-dimensional geometry of the trench corners locally modulates the oxidation rate [A2]. Specifically, a small bird's beak forms in the pad oxide under the nitride edge, which increases the radius of curvature at the top active area corners [P2]. This geometric rounding is essential to prevent electric field crowding at sharp corners, thereby eliminating the parasitic edge transistor conduction that causes the subthreshold Id-Vg double-peak phenomenon [P3]. Additionally, the high-temperature thermal cycle facilitates atomic diffusion and lattice relaxation, effectively releasing residual mechanical stress induced by both the silicon etch and the overlying SiN hardmask [A1]. Thermal oxidation is explicitly selected over deposited oxides for this initial liner because the physical consumption of substrate silicon inherently removes the outermost layer of defective etched silicon [A2]. The process temperature and ambient gas mixture are carefully tuned to optimize the corner rounding effect while minimizing the lateral encroachment into the active area [P3]. Utilizing a high-temperature thermal cycle during liner growth allows for volumetric stabilization and stress relaxation at an early stage, which significantly reduces the subsequent thermo-mechanical stress generated when the bulk trench is filled with CVD oxides [P1]. Parameter interactions dictate that higher oxidation temperatures enhance the viscous flow of the grown oxide and promote silicon lattice relaxation, which suppresses the formation of stress-induced dislocations along <111> slip planes [P1]. For a nanoscale Backside Illuminated (BSI) CIS technology, the physical dimensions of the STI structure are highly scaled, leading to increased volume fractions of isolation material and proportionately higher mechanical stress [P1]. If this stress is not adequately managed during the liner oxidation phase, it will induce silicon dislocations that propagate into the photodiode depletion regions, creating parasitic junction leakage paths [P1]. Such stress-induced leakage current (SILC) directly translates to severe dark current and white pixel defects, which catastrophically degrade image sensor performance [P1]. Therefore, completing volume stabilization and stress relief via liner oxidation before trench fill is a mandatory process evolution to maintain yield and reliability at advanced nodes [P1].