40nm BSI CMOS Image SensorPreview

Wet Deglaze Etch

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SiN Strip

Blanket B Well Implant
25SiN Hard Mask Deposition26SiO Hard Mask Deposition27Pre Litho Cleaning28Shallow Trench Isolation - Photo29Oxide Etch30Nitride Etch31Si Etch32Ashing & Strip/Clean33Trench Sidewall Passivation34STI Liner Oxidation35STI Fill Conformal CVD Liner36STI Fill Liner Etchback37Oxidation Preaclean38STI Fill Conformal CVD Oxide39STI Fill Post Clean40STI Conformal CVD Anneal41Pre-CMP Oxide Deposition42STI CMP43STI CMP Post Cleaning44STI Final Densification Anneal45Wet Deglaze Etch46SiN Strip47Blanket B Well Implant

Process Cross-Section

STI · S22 · Surface SiN Hard Mask Strip (DTI Fill Retained)SiO2 liner (SACVD)SiO2 (SACVD bulk fill)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)SiNSi

Step highlight

The stripping process must be highly selective to avoid consuming the adjacent planarized STI oxide and the underlying pad oxide .

In depth

The silicon nitride (SiN) layer functions as a rigid hard mask during shallow trench isolation (STI) patterning and acts as a robust stop layer during chemical-mechan

ical planarization (CMP) . Following the STI Final Densification Anneal and Wet Deglaze Etch, this SiN layer must be entirely removed to expose the active silicon regions . This removal process prepares the substrate for the subsequent Blanket B Well Implant and thermal gate oxide growth steps . The stripping process must be highly selective to avoid consuming the adjacent planarized STI oxide and the underlying pad oxide . Without this precise removal, residual nitride would block subsequent dopant implantation and prevent the formation of the uniform complementary MOS (CMOS) channel structures required for device operation . The fundamental chemical mechanism relies on wet etching using a high-temperature phosphoric acid (H3PO4) aqueous solution . In this environment, solid Si3N4 undergoes a hydrolysis reaction to form soluble orthosilicic acid (Si(OH)4) . This dissolution is governed by chemical thermodynamic equilibrium and reaction kinetics, featuring a reversible dehydration pathway where Si(OH)4 can convert into metasilicic acid and eventually precipitate as solid SiO2 . According to Le Chatelier's principle, the accumulation or deliberate addition of Si(OH)4 in the solution shifts the equilibrium to suppress the further dissolution of solid SiO2 . This thermodynamic shift establishes an intrinsically high etch selectivity for SiN over SiO2, allowing the thin pad oxide to act as a flawless etch-stop layer . Wet chemistry is chosen over plasma dry etching because dry etching processes, despite their anisotropic precision, lack the near-infinite material selectivity required to perfectly preserve the STI oxide height and pad oxide integrity . During the wet etch, temperature and water concentration act as the primary control parameters determining heat transfer, mass transfer, and reaction equilibrium . Increasing the bath temperature exponentially accelerates the Si3N4 reaction kinetics but simultaneously decreases the solubility and stability of the Si(OH)4 byproduct, introducing a severe risk of solid SiO2 precipitation . To counteract evaporation and maintain the boiling point of the mixture, deionized water is continuously spiked into the solution, regulating the dynamic etching equilibrium (Engineering Practice). In single-wafer processing architectures, spray-induced heat loss can cause rapid local cooling and increased acid viscosity, necessitating the use of upper heating plates to maintain the strict thermodynamic balance . For 40nm BSI CMOS Image Sensors, strict preservation of the STI step height is critical because mechanical stress from the isolation trench directly affects localized carrier mobility and subthreshold leakage . Any loss of STI oxide during the SiN strip compromises the engineered rounding of the top trench corners . If these corners are exposed due to poor etch selectivity, localized electric field crowding occurs, which drastically amplifies stress-induced leakage current and parasitic subthreshold conduction . Therefore, precisely controlled hot phosphoric wet etching is mandatory to strip the SiN without degrading the delicate isolation structures, ensuring pixel performance and minimizing dark current generation .

Risks & Challenges

  • [High] SiO2 Precipitation and Particle Contamination: At elevated phosphoric acid temperatures, the solubility of the Si(OH)4 byproduct decreases . If the local temperature fluctuates or the silicate concentration exceeds the thermodynamic solubility limit, the reversible dehydration reaction forces SiO2 to precipitate out of the solution . These colloidal particles can deposit onto the active wafer surface, acting as micromasking defects during the subsequent Blanket B Well Implant and causing severe yield loss (Engineering Practice).
  • [Medium] STI Oxide Recess and Corner Exposure: The high etch selectivity of SiN to SiO2 relies heavily on maintaining a specific concentration of dissolved silicate in the etchant . If the acid is under-seasoned (lacking sufficient initial silicate) or the water spiking ratio is poorly controlled, the solution will begin to etch the protective STI oxide . This unintended oxide loss exposes the sharp silicon trench corners, leading to electric field enhancement and an increase in both radiation-induced and voltage-induced parasitic subthreshold leakage .
  • [Medium] Incomplete SiN Removal (Residues): The Si3N4 etch rate in phosphoric acid is highly sensitive to the etchant temperature and local fluid viscosity . In single-wafer processing, spray-induced heat loss can cause rapid local cooling and increased acid viscosity on the wafer surface, severely retarding the reaction kinetics . Remaining SiN residues act as an unintended mask blocking the subsequent well implants, which locally shifts the threshold voltage and degrades pixel-to-pixel uniformity in the image sensor array .
  • [Low] Substrate Silicon Pitting: The thin pad oxide beneath the SiN layer is designed to act as a definitive etch stop to protect the underlying crystalline silicon . If anomalous oxide etching occurs due to a failure in the chemical selectivity mechanism, the pad oxide may be completely breached (Engineering Practice). Exposure of the bare silicon substrate to hot phosphoric acid results in localized crystallographic pitting, which introduces surface states and defects that drastically reduce the reliability and breakdown voltage of the future gate oxide .

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Related steps

  • SiN Hard Mask Deposition
  • SiO Hard Mask Deposition
  • Pre Litho Cleaning
  • Shallow Trench Isolation - Photo
  • Oxide Etch
  • Nitride Etch