Chemical oxidants condition the passivated surface, while complexing agents dissolve the oxidized species into soluble complexes .
In depth
Following the anisotropic Silicon Etch step that defines the shallow trench boundaries, the wafer surface and trench sidewalls are inevitably coated with post-plasma
etch residues, including silicon oxychloride passivating films and halogen-rich polymers . This specific Ashing & Strip/Clean step is critically positioned to eradicate these byproducts and restore the pristine crystalline silicon state of the trench before proceeding to Trench Sidewall Passivation and STI Liner Oxidation . Unlike subsequent back-end strip steps that must protect metal interconnects or low-k dielectrics from corrosion , this front-end step acts directly on the exposed active silicon . It must completely remove organic and inorganic etch byproducts without inducing surface roughening, which would degrade the subsequent thermal liner oxide quality and aggravate edge-leakage or parasitic conduction in the final device . Failure to achieve a perfectly clean interface will generate localized trap states at the STI boundary, leading to severe dark current generation—a critical performance detractor in CMOS image sensors . The process fundamentally operates through a sequential dual-mechanism approach: plasma-assisted oxidation (ashing) followed by wet-chemical dissolution (strip/clean) . During the ashing phase, energized oxygen or forming-gas radicals react with the carbonaceous backbone of the photoresist and polymeric residues, breaking chemical bonds and volatilizing them as gaseous byproducts such as CO2 and H2O (Engineering Practice). Subsequently, the wet-cleaning phase targets the inorganic residues, primarily the silicon oxychloride sidewall passivation that was deliberately formed by the Cl2/O2 silicon etch chemistry to maintain profile anisotropy . Drawing on wet-chemical semiconductor processing principles, this involves a carefully balanced oxidation and dissolution sequence . Chemical oxidants condition the passivated surface, while complexing agents dissolve the oxidized species into soluble complexes . The dissolution rate is heavily governed by surface chemical reaction kinetics rather than hydrodynamic mass transport, which ensures uniform residue removal even within the high-aspect-ratio sub-micron trenches . The selection of specific cleaning chemistries must precisely balance comprehensive residue removal with the absolute preservation of the exposed silicon trench geometry and the surviving pad nitride hardmask . While highly aggressive chemistries could rapidly clear the chlorocarbon polymers, they risk isotropic etching of the bare silicon walls . This would alter the strictly controlled trench sidewall angle (designed to be >80°) and degrade the rounded trench bottom needed to prevent electric field crowding and stress concentration . Therefore, highly selective wet formulations are utilized, leveraging principles of controlled chemical complexation and selective adsorption to differentiate between the residue and the substrate . Parameter interactions, such as bath temperature, oxidant concentration, and immersion time, directly modulate the etch selectivity and define the final atomic-scale surface smoothness . A kinetically controlled processing window is maintained to prevent localized over-etching at underlying crystal defects, which would otherwise induce nanoscale surface roughening . In the context of a 40nm BSI CMOS Image Sensor, the physical dimensions of the active area pitch are extremely scaled, significantly amplifying the mechanical stress exerted by the STI structure on the silicon channel . Any localized silicon loss or micro-trenching introduced during this cleaning step will act as a geometric stress concentrator during the subsequent high-temperature gap-fill and densification processes . Furthermore, because photo-generated charge carriers in BSI sensors are exceptionally sensitive to surface recombination at the STI-to-active area boundaries, achieving an atomically smooth, defect-free trench sidewall is mandatory to suppress parasitic dark current and white pixel defects .
Risks & Challenges
[High] Incomplete Halogen Polymer Removal: If the plasma ashing or wet chemical oxidation is insufficient, residual chlorocarbon polymers or silicon oxychloride from the Si Etch step will remain on the trench sidewalls . During subsequent high-temperature liner oxidation, these halogenated residues will decompose and incorporate into the growing thermal oxide, generating dense interface trap states that cause severe parasitic edge leakage and increased dark current in the image sensor pixels .
[High] Silicon Sidewall Roughening and Pitting: Excessive oxidant concentration or overly prolonged wet etch times can transition the cleaning mechanism from residue dissolution to active silicon attack . This localized etching is highly sensitive to crystal defects and will create nanoscale surface roughening, which subsequently concentrates electric fields and mechanical stress, leading to transistor Id-Vg double-peak phenomena .
[Medium] Pad Nitride Hardmask Erosion: If the wet clean chemistry lacks sufficient selectivity between the post-etch residues and the silicon nitride capping layer, the hardmask will be thinned . Premature loss of the pad nitride compromises the chemical mechanical polishing (CMP) stop margin in downstream steps, potentially leading to active area erosion and degraded STI planarity .
[Low] STI Trench Bottom Profile Deformation: Aggressive chemical attack at the intersection of the trench bottom and the sidewall can sharpen the geometrically rounded corners established during the Si Etch . Loss of this curvature drastically increases the local mechanical stress during subsequent HDP or CVD oxide gap-fill, potentially inducing dislocations in the silicon lattice that degrade carrier mobility .