40nm BSI CMOS Image SensorPreview

the underlying silicon nitride (SiN) pad layer [P2]. During the chemical mechanical polishing process, residual oxide often remains on top of the SiN pad, or the STI oxide requires a slight recess to prepare for the subsequent SiN strip [A2]. The Wet Deglaze Etch removes this residual oxide layer, ensuring that the subsequent hot-phosphoric acid bath can uniformly access and remove the SiN layer without being blocked by oxide micro-masking [P2]. If the oxide is not completely deglazed, the SiN strip will be uneven, potentially disrupting the subsequent blanket B well implant and well oxide growth steps [A2]. The deglaze process relies on the wet chemical dissolution of silicon dioxide, typically using a highly selective hydrofluoric acid (HF) based solution [P4]. The core mechanism involves the chemical reaction of the etchant with the oxide surface, operating as a kinetically controlled surface reaction rather than a mass-transport limited process [P4]. Because the prior step is a high-temperature densification anneal, the STI gap-fill oxide has undergone structural rearrangement and visco-elastic relaxation [P3]. This densification ensures that the HF etch proceeds isotropically and at a predictable rate across the STI structure, avoiding the rapid, localized etching that occurs in unannealed or highly porous dielectric films [P1]. Similar to the strong HF wet etch used to remove pad oxides and recess shallow trench isolation structures, this deglaze step precisely defines the final dielectric topography [A1]. A wet-chemical approach is selected over dry reactive ion etching because it provides nearly infinite selectivity to the underlying SiN pad layer, preventing plasma-induced damage to the active area structures [P1]. Wet processing provides mild, damage-free surface conditioning that is essential for maintaining smooth interfaces in advanced semiconductor manufacturing [P4]. Process parameters such as etchant concentration, temperature, and immersion time are carefully tuned to control the exact amount of oxide removed [P4]. Controlling the deglaze time directly determines the final step height between the STI oxide and the active silicon area, which is a critical geometric parameter for minimizing corner electric field peaks [P2]. In 40nm BSI CMOS Image Sensors, precise control of the STI recess during deglaze is paramount to avoid exposing the active area trench corners [P1]. Over-etching the STI oxide exposes these sharp trench corners, which locally enhances the electric field and makes the device highly sensitive to charge trapping and parasitic channel turn-on [P2]. This parasitic conduction degrades pixel leakage and dark current performance, which are strictly budgeted in image sensor technology (Engineering Practice). Therefore, the wet deglaze must be tightly coupled with the densification anneal's stress modulation to ensure the oxide removal remains highly uniform across both isolated and dense active area arrays [P3].