The chemical kinetics must account for the rapid dissolution rate of the unannealed oxide, ensuring that only the uppermost contaminated monolayers are stripped away .
In depth
The STI Fill Post Clean is a critical wet processing step positioned immediately after the deposition of the STI conformal CVD ox
ide and prior to the high-temperature densification anneal . The upstream conformal CVD process, which may utilize TEOS-O3 or flowable CVD (FCVD) techniques, leaves the trench filled with an initially low-density, metastable dielectric network [P1, P3]. If airborne contaminants, metallic traces, or loosely bound particles from the deposition chamber remain on this surface, the subsequent high-temperature anneal will drive these impurities deep into the oxide matrix . By removing these residues, the post clean ensures that the isolation dielectric achieves a high-purity composition during the densification phase, which is essential for suppressing localized leakage and field-enhanced parasitic conduction at the trench edges [P1, T1]. The cleaning mechanism operates through highly controlled chemical etching and oxidation-reduction reactions tailored to a low-density dielectric surface . As-deposited CVD oxides, particularly flowable CVD films, often contain incompletely reacted species such as Si-N and Si-OH, making them structurally porous and highly susceptible to chemical attack . Therefore, the post clean utilizes a carefully balanced chemistry, typically involving highly dilute acidic or standard cleaning sequences, to lift off particles without causing excessive erosion of the delicate as-deposited film (Engineering Practice). The chemical kinetics must account for the rapid dissolution rate of the unannealed oxide, ensuring that only the uppermost contaminated monolayers are stripped away . This precise removal prevents the formation of deep surface pits that could nucleate voids or weak seams during the subsequent pre-CMP oxide deposition and planarization steps [P1, P2]. The selection of cleaning chemistries is dictated by the chemical instability and material dependence of the unannealed CVD oxide . Because the oxide has not yet undergone visco-elastic relaxation or structural rearrangement via high-temperature annealing, aggressive etchants would uncontrollably alter the trench fill profile and potentially expose the underlying silicon corners [P4, P1]. By modulating the concentration of the cleaning agents and the process temperature, engineers can minimize the chemical etch rate of the metastable network while maximizing particle removal efficiency . Furthermore, controlling the time delay (aging) between the CVD deposition and the wet clean/anneal sequence can influence the film's resistance to the cleaning chemistry, as ambient moisture progressively reacts with the film to increase its network connectivity . This interaction between film aging and clean selectivity ensures that the structural integrity of the STI module is maintained prior to the final steam or inert anneal [P3, P4]. In nanoscale Backside Illuminated (BSI) CMOS Image Sensors, minimizing dark current and white pixel defects requires near-perfect defect management at all isolation interfaces . The aggressive pitch scaling in the 40nm node necessitates high-aspect-ratio trench fills where stress concentration at the STI corners can severely degrade local carrier generation and mobility [P1, P4]. Any non-uniformity introduced by an overly aggressive post clean will exacerbate volumetric shrinkage during the subsequent anneal, amplifying mechanical stress in the adjacent active silicon . Therefore, this post clean must be exceptionally mild to preserve the designed gap-fill geometry and prevent stress-induced leakage currents that directly compromise image sensor performance [P1, P4].
Risks & Challenges
[High] Excessive Film Loss and Profile Degradation: Because as-deposited CVD oxides (especially TEOS-O3 or FCVD) exhibit low density and contain unreacted species like Si-N, their wet etch rates are significantly higher than those of thermal oxides [P1, P3]. An improperly calibrated post clean chemistry will excessively etch the trench fill, altering the isolation geometry and potentially re-exposing the rounded trench corners . This leads to electric field concentration and parasitic edge conduction in the final device .
[High] Impurity Drive-in from Incomplete Cleaning: If the post clean fails to completely remove surface particles or metallic contaminants from the CVD deposition chamber, the subsequent high-temperature densification anneal will drive these impurities into the oxide matrix . This creates localized charge traps within the STI dielectric, which degrades the isolation margin and increases device leakage [P1, T1].
[Medium] Stress-Induced Defect Nucleation: Non-uniform etching during the clean can create surface roughening or micro-trenches in the metastable oxide . During the subsequent thermal densification, the structural rearrangement and volumetric shrinkage of this roughened film will generate uneven mechanical stress on the surrounding silicon active area . This localized stress concentration can nucleate dislocations, leading to increased diode leakage or degraded carrier mobility [P1, P4].
[Low] Moisture Absorption and Film Swelling: Prolonged exposure to aqueous cleaning solutions without rapid drying or immediate transfer to the annealing furnace can cause the unannealed, porous CVD film to absorb excessive water . This alters the chemical composition of the film and can lead to violent outgassing or micro-cracking during the rapid temperature ramp-up of the subsequent thermal anneal (Engineering Practice).