40nm BSI CMOS Image SensorPreview

STI Fill Liner Etchback

37/ 417

Oxidation Preaclean

STI Fill Conformal CVD Oxide
25SiN Hard Mask Deposition26SiO Hard Mask Deposition27Pre Litho Cleaning28Shallow Trench Isolation - Photo29Oxide Etch30Nitride Etch31Si Etch32Ashing & Strip/Clean33Trench Sidewall Passivation34STI Liner Oxidation35STI Fill Conformal CVD Liner36STI Fill Liner Etchback37Oxidation Preaclean38STI Fill Conformal CVD Oxide39STI Fill Post Clean40STI Conformal CVD Anneal41Pre-CMP Oxide Deposition42STI CMP43STI CMP Post Cleaning44STI Final Densification Anneal45Wet Deglaze Etch46SiN Strip47Blanket B Well Implant

Process Cross-Section

STI · S13 · Oxidation Pre-CleanSiO2SiNSiO2 liner (SACVD)keyhole (pre bulk-fill)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)Si

Step highlight

By preparing a completely clean interface, the process directly supports the suppression of parasitic conduction and leakage required for deep-submicron devices .

In depth

Following the STI liner etchback, the trench surfaces and corners are exposed to plasma, often leaving behind fluorocarbon polymers, m

etallic contaminants, or damaged silicon . Before the high-quality conformal CVD oxide is deposited to fill the trench, the surface must be meticulously cleaned to prevent trapped interfacial charge or structural defects . This preclean step ensures that the subsequent CVD oxide interfaces with a pristine surface, which is critical for maintaining robust electrical and structural isolation between adjacent active regions . By preparing a completely clean interface, the process directly supports the suppression of parasitic conduction and leakage required for deep-submicron devices . The wet clean operates by utilizing a sequence of chemical reactions to selectively remove contaminants without excessively etching the exposed silicon or the delicate STI liner (Engineering Practice). Oxidizing agents chemically oxidize the bare silicon surface, forming a sacrificial chemical oxide layer that lifts off particulate and metallic contaminants . Dilute hydrofluoric acid is then typically used to strip this chemical oxide, exposing a clean, hydrogen-terminated silicon interface (Engineering Practice). Simultaneously, careful control of the chemical etch rate allows for a slight adjustment of the pad oxide undercut, which interacts synergistically with subsequent high-temperature oxidation or deposition steps to promote corner rounding . Managing the structural geometry through this surface conditioning is crucial, as sharp corners enhance local electric fields and cause parasitic transistor double-peak phenomena . Wet cleaning is selected over dry plasma processes because it provides highly isotropic and selective chemical etching, ensuring uniform treatment of high aspect-ratio trenches without introducing plasma-induced physical damage . The process parameters, such as chemical concentration and immersion time, are strictly controlled to balance contaminant removal efficiency against the risk of over-etching the existing liner oxide . Excessive etching during this step would thin the protective liner, exposing the active silicon region to high compressive thermal stresses generated during the subsequent oxide fill and densification . These residual stresses must be managed meticulously because they can alter carrier mobility via silicon piezoresistive effects and shift the threshold voltage due to deformation potential-induced band level modifications . In nanoscale Backside Illuminated (BSI) CMOS Image Sensors, active area pitch scaling demands extremely tight control of trench dimensions and interface trap densities . Any residual metallic contamination or unpassivated dangling bonds at the STI interface act as generation-recombination centers, resulting in increased dark current and white pixel defects . Therefore, the oxidation preclean must achieve ultra-low trace metal levels while strictly preserving the rounded trench bottom and corner profiles required to minimize stress concentration and gate field enhancement .

Risks & Challenges

  • [High] Incomplete Polymer/Residue Removal: Failure to fully remove plasma etchback residues prevents the conformal CVD oxide from adhering properly . This creates localized voids or seams during the trench fill process, which degrade the dielectric structural integrity and isolation margin .
  • [High] Excessive Pad Oxide Undercut / Liner Loss: Overly aggressive cleaning chemistry etches too much of the existing liner or pad oxide, directly affecting the STI dimensional control . This exposes sharp silicon corners, leading to electric field concentration that causes parasitic conduction and the transistor double-peak effect . Furthermore, inadequate liner thickness exacerbates layout-dependent compressive stresses from the CVD fill, severely shifting device mobility and threshold voltage .
  • [Medium] Metallic Contamination Re-deposition: Depleted or unbalanced cleaning baths can cause metallic ions to precipitate back onto the silicon surface (Engineering Practice). These metals create deep-level energy states inside the bandgap as described by fundamental semiconductor physics , acting as dark current sources that are catastrophic for BSI CMOS image sensors (Engineering Practice).
  • [Low] Surface Roughening: An unbalanced oxidation-etch cycle in the wet chemistry can cause micro-roughening of the silicon trench sidewalls . Rough interfaces introduce localized stress concentration points that nucleate crystalline defects in the silicon island during subsequent thermal treatments .

Sign in to continue through all 417 steps

Sign up with emailLog in

Related steps

  • SiN Hard Mask Deposition
  • SiO Hard Mask Deposition
  • Pre Litho Cleaning
  • Shallow Trench Isolation - Photo
  • Oxide Etch
  • Nitride Etch