After anisotropic silicon etching and subsequent photoresist stripping and cleaning, the shallow trench isolation (STI) sidewalls and bottom are left with disrupted lattice structures and highly reactive dangling bonds P4.The Trench Sidewall Passivation step is introduced immediately prior to the formal STI Liner Oxidation to condition this raw silicon surface P1.In a 40nm BSI CMOS Image Sensor, mitigating dark current and white pixel defects is critical, making the elimination of surface states