Trench Sidewall Passivation - 40nm

Any trap states or dislocations intersecting the junction depletion region act as severe leakage sources, directly degrading device performance by providing paths for stress-induced leakage current .

After anisotropic silicon etching and subsequent photoresist stripping and cleaning, the shallow

trench isolation (STI) sidewalls and bottom are left with disrupted lattice structures and highly reactive dangling bonds . The Trench Sidewall Passivation step is introduced immediately prior to the formal STI Liner Oxidation to condition this raw silicon surface . In a 40nm BSI CMOS Image Sensor, mitigating dark current and white pixel defects is critical, making the elimination of surface states and etch-induced defects paramount . By passivating the surface—often through a mild thermal treatment or light radical oxidation—this step prevents uncontrolled native oxide growth and stabilizes the surface chemistry, establishing a uniform nucleation foundation for the subsequent conformal thermal liner oxide . During the preceding plasma etch, high-energy ion bombardment physically sputters the silicon, breaking covalent bonds and leaving an amorphous, defect-rich surface layer . Passivation chemically satisfies these dangling bonds, typically by forming a transient, ultra-thin passivating layer that terminates the silicon lattice . Furthermore, the STI etching process combined with the silicon nitride hard mask introduces significant mechanical stress into the silicon substrate . Thermomechanical stress concentrated at trench sidewalls and bottom corners can induce silicon dislocations that propagate along <111> slip planes, ultimately acting as generation-recombination centers for stress-induced leakage current (SILC) . The passivation step, which may incorporate a localized thermal relaxation or surface treatment, initiates lattice recovery and stress redistribution, effectively reducing the thermodynamic driving force for dislocation generation during subsequent high-thermal-budget processes . The choice of passivation method balances the need for surface repair against thermal budget constraints, utilizing either low-temperature radical surface treatments or controlled rapid thermal anneals . Methods involving specific surface treatments, such as introducing selected atomic species, can alter the local lattice structure and convert or modulate intrinsic stress distributions . Parameter interaction is tightly coupled: increasing the treatment temperature or radical flux enhances bond termination and lattice relaxation, but excessive energy may prematurely consume active silicon or alter the designed trench sidewall angle . Therefore, the process parameters must be precisely tuned to maximize stress relief and defect annealing without compromising the critical trench geometric profile required for sub-micron isolation . At the 40nm node, the increased aspect ratio of the STI structures and the dense array layout amplify the impact of mechanical stress on carrier mobility and leakage . Any trap states or dislocations intersecting the junction depletion region act as severe leakage sources, directly degrading device performance by providing paths for stress-induced leakage current . Implementing a dedicated passivation step ensures that the silicon-dielectric interface is pristine before the liner oxide is grown, facilitating ideal corner rounding and preventing electric field concentration that causes parasitic conduction .

[High] Incomplete Lattice Repair / Residual Etch Damage: If the passivation energy or time is insufficient, residual amorphous silicon and dangling bonds from the plasma etch will persist . This leads to a poor-quality interface during the subsequent STI liner oxidation, creating trap states that generate stress-induced leakage current and elevate dark current in the image sensor .
[Medium] Excessive Surface Consumption / Dimensional Shift: An overly aggressive passivation treatment can consume too much silicon, inadvertently altering the critical trench sidewall angle and increasing the trench width . If the sidewall angle drops below the design threshold, it reduces the effective isolation depth and compromises inter-pixel electrical isolation at narrow pitches .
[Medium] Stress-Induced Dislocation Propagation: Improper control of the thermal gradient during the passivation step can fail to properly relieve the structural stress imparted by the SiN hard mask and the trench geometry . Unrelieved localized stress at the trench corners will trigger silicon dislocations to propagate along specific slip planes, leading to fatal junction leakage .
[Low] Surface Contamination / Uncontrolled Native Oxidation: If the passivation environment is not strictly controlled, the highly reactive dangling bonds on the freshly etched silicon surface may absorb impurities or form irregular native oxides . This non-uniform layer disrupts the uniform growth kinetics of the subsequent thermal liner oxidation, potentially causing localized oxide thinning and premature dielectric breakdown .

Any trap states or dislocations intersecting the junction depletion region act as severe leakage sources, directly degrading device performance by providing paths for stress-induced leakage current .

After anisotropic silicon etching and subsequent photoresist stripping and cleaning, the shallow

[High] Incomplete Lattice Repair / Residual Etch Damage: If the passivation energy or time is insufficient, residual amorphous silicon and dangling bonds from the plasma etch will persist . This leads to a poor-quality interface during the subsequent STI liner oxidation, creating trap states that generate stress-induced leakage current and elevate dark current in the image sensor .
[Medium] Excessive Surface Consumption / Dimensional Shift: An overly aggressive passivation treatment can consume too much silicon, inadvertently altering the critical trench sidewall angle and increasing the trench width . If the sidewall angle drops below the design threshold, it reduces the effective isolation depth and compromises inter-pixel electrical isolation at narrow pitches .
[Medium] Stress-Induced Dislocation Propagation: Improper control of the thermal gradient during the passivation step can fail to properly relieve the structural stress imparted by the SiN hard mask and the trench geometry . Unrelieved localized stress at the trench corners will trigger silicon dislocations to propagate along specific slip planes, leading to fatal junction leakage .
[Low] Surface Contamination / Uncontrolled Native Oxidation: If the passivation environment is not strictly controlled, the highly reactive dangling bonds on the freshly etched silicon surface may absorb impurities or form irregular native oxides . This non-uniform layer disrupts the uniform growth kinetics of the subsequent thermal liner oxidation, potentially causing localized oxide thinning and premature dielectric breakdown .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges