As the underlying silicon is exposed, the system relies on an intrinsic chemical competition between etching and surface polymerization to prevent substrate loss .
The pad oxide etch step serves as the final breakthrough process in the contact formation module, removing a thin protective dielectr
ic layer to expose the underlying active silicon or polysilicon gate . This step sequentially follows the bulk Pre-Metal Dielectric (PMD) etch and the Contact Etch Stop Layer (CESL) opening (Engineering Practice). Unlike the earlier PMD oxide etch, which is designed for high-rate removal of thick dielectric materials in high aspect ratio structures, the pad oxide etch targets only a very thin residual layer and demands extreme selectivity to the underlying substrate . Completely clearing this oxide to expose a pristine semiconductor surface is an absolute prerequisite for the subsequent Ti/TiN barrier deposition, which requires an intimate interface to minimize spreading resistance and form a near-ideal metal-semiconductor contact . Physically, the pad oxide etch employs a reactive ion etching (RIE) framework where neutral radicals and directionally accelerated ions react synergistically with the wafer surface . In a fluorocarbon-based plasma system, free fluorine species chemically attack the Si-O bonds, generating volatile byproducts such as SiFx and COx to efficiently clear the oxide . As the underlying silicon is exposed, the system relies on an intrinsic chemical competition between etching and surface polymerization to prevent substrate loss . Fluorocarbon radicals (CFx) deposit a carbon-rich passivation film selectively on the silicon surface, which sterically hinders incoming fluorine atoms and drastically suppresses the silicon etch rate . Meanwhile, keeping the extraction potential and resulting ion energy low is strictly necessary to prevent energetic ions from inducing physical lattice damage or implanting into the junction space . The choice of fluorocarbon chemistries, frequently modified with hydrogen-bearing additives, is governed by the need to shift the plasma chemistry toward a higher C/F ratio, thereby enhancing the polymer film formation rate on silicon without heavily degrading the oxide etch rate . RF bias power and chamber pressure are carefully balanced; lower bias voltages reduce the physical sputtering yield and minimize subsurface defect generation . Additionally, the residence time of the reactive species in the chamber is controlled to stabilize the equilibrium between radical dissociation and polymer deposition, serving as a primary knob for tuning the final SiO2-to-Si selectivity . For 40nm CMOS Image Sensor technology, transistor scaling requires exceptionally shallow source/drain extensions to maintain gate control and suppress subthreshold leakage currents . If the pad oxide etch is insufficiently selective and consumes the highly doped surface silicon, it removes the critical region needed for low-resistance silicide formation, severely increasing contact resistance . Furthermore, uncontrolled plasma bombardment introduces mid-gap trap states and dangling bonds into the semiconductor lattice . These etch-induced defects act as localized generation-recombination centers that increase reverse-bias leakage, fundamentally compromising the subthreshold thermodynamic limits and degrading the pixel dark current performance .
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