40nm BSI CMOS Image SensorPreview

the thick composite inter-layer dielectric (ILD6) in the upper back-end-of-line (BEOL) of a 40nm BSI CMOS Image Sensor [P1]. Following the Ta-Barrier etch and photoresist ashing at the bondpad level, the ILD structure must be built up incrementally to encapsulate the underlying interconnects and prepare for subsequent planarization and via formation [A2]. Multi-stage deposition (e.g. (Engineering Practice), advancing from ILD 6-3 to 6-4) is utilized to manage the accumulation of intrinsic film stress and to prevent premature void closure in narrow gaps, consistent with the thick ILD integration schemes demonstrated in [P1]. Because this layer sits near the top of the BEOL stack, it must provide mechanical support and isolate the metal lines from environmental factors while adhering to stringent thermal budget constraints to protect existing structures [P3]. The deposition typically employs plasma-enhanced chemical vapor deposition (PECVD) utilizing a tetraethoxysilane (TEOS) precursor to ensure a highly conformal dielectric film at low temperatures [P4]. In this process, reactive oxygen species generated by the plasma interact with TEOS molecules adsorbed on the wafer surface, driving oxidation and the formation of a rigid SiO2 network [P4]. Because the reaction is governed by surface adsorption and desorption equilibrium rather than purely thermal decomposition, the surface diffusion time is sufficient to allow precursor migration into complex topographical features, resulting in excellent step coverage [P4]. To address high aspect ratios between metal lines, high-density plasma techniques may also be incorporated, relying on simultaneous deposition and argon sputtering to keep gap entrances open and achieve void-less dielectric filling [P1]. TEOS-based oxide is selected for ILD 6-4 because its low deposition temperature (<400°C) preserves the structural integrity of the underlying copper or aluminum metallization, which are highly sensitive to thermal degradation [P4]. While lower BEOL layers often employ porous low-k dielectrics to reduce interconnect RC delay [P2], top-level ILDs prioritize mechanical robustness, breakdown strength, and moisture resistance to mitigate stress-induced voiding (SIV) and time-dependent dielectric breakdown (TDDB) [P3]. Parameters such as the O2-to-TEOS ratio and RF power directly dictate the concentration of active oxygen radicals, thereby controlling the deposition rate and the structural density of the final SiO2 network [P4]. In 40nm technology, the reduced metal spacing and line widths substantially increase local electric fields and thermo-mechanical stress gradients within the BEOL [P3]. Consequently, the ILD stack must not only isolate the interconnects but also exhibit sufficient mechanical rigidity to counteract momentum transfer from charge carriers during high-current operation, thereby suppressing electromigration [P3]. Segmenting the ILD6 deposition into multiple sub-steps allows for intermediate stress relaxation and finer control over the total film thickness, ensuring compatibility with subsequent chemical mechanical polishing (CMP) and lithography steps (Engineering Practice).