Pre Litho Cleaning - 40nm

Its primary objective is to remove adventitious airborne molecular contaminants (AMCs), organic trace residues, and nanoscale particles without altering the thickness or chemical composition of the underlying ILD 3-2 oxide layer .

The Pre Litho Cleaning step in the ILD3 module is critically posi

tioned between the deposition of the ILD 3-2 dielectric layer and the Via 3 (V3) photolithography patterning step (Engineering Practice). Unlike post-CMP cleaning steps that must remove heavy metallic contamination, or post-etch cleans that target heavily crosslinked fluorocarbon polymer residues , this specific pre-litho clean addresses a freshly deposited dielectric surface (Engineering Practice). Its primary objective is to remove adventitious airborne molecular contaminants (AMCs), organic trace residues, and nanoscale particles without altering the thickness or chemical composition of the underlying ILD 3-2 oxide layer . By restoring a uniform baseline surface energy across the wafer, this step ensures optimal wetting, uniform coating, and strong interfacial adhesion of the subsequent bottom anti-reflective coating (BARC) and photoresist layers . The core physical-chemical mechanism relies on mild oxidative dissolution to eliminate organic contaminants without resorting to aggressive dry plasma treatments that could induce bond scission and polar group formation in the dielectric . A common approach utilizes dissolved ozone (DIO3) in deionized water to create a highly reactive oxidative environment . The ozone molecules and their decomposition-generated oxygen radicals preferentially attack the –CH2– backbone structures of organic trace contaminants . This initiates carbon-chain scission, ultimately oxidizing the organics into volatile CO2 and H2O . To complement the chemical oxidation, megasonic acoustic waves are frequently coupled into the cleaning fluid to generate cavitation and microjets . This physical phenomenon enhances the mass transport of the reactive chemical species through the liquid boundary layer and provides the mechanical force necessary to overcome van der Waals forces, thereby dislodging tightly bound nanoparticles . Material and chemistry selection heavily favors dilute aqueous oxidants over traditional sulfuric acid/hydrogen peroxide mixtures (SPM), as SPM is highly corrosive, poses severe safety risks, and can degrade advanced dielectric films . In some advanced formulations, the introduction of specific trace metal ions or buffering agents into the water-soluble solvent system is used to fine-tune the interfacial chemical interactions . This regulates the ionic strength and surface adsorption behavior, suppressing unwanted chemical attack on the low-k or porous dielectric layers while maintaining organic removal efficiency . Process control centers on parameters such as ozone concentration, gas-liquid contact time, and megasonic power . Higher ozone solubility accelerates oxidation rates, while optimized megasonic power maximizes mass transport without reaching cavitation intensities that could physically pit the dielectric surface . At the 40nm node, the stringent requirements for via resolution and critical dimension (CD) uniformity mandate an exceptionally pristine surface prior to lithography (Engineering Practice). Because the underlying ILD3 stack often incorporates complex materials or porous structures to minimize parasitic capacitance, any chemical process must strictly avoid moisture ingress or chemical modification that could increase the dielectric constant . Therefore, this pre-litho clean must perfectly balance ultra-high defect removal efficiency with near-zero substrate consumption, setting the foundation for accurate Via 3 pattern transfer (Engineering Practice).

[High] Photoresist Adhesion Failure: Incomplete oxidation and removal of organic contaminants due to insufficient ozone concentration or gas-liquid contact time leaves hydrophobic residues on the dielectric . This localized low surface energy prevents proper BARC wetting, leading to resist peeling or pattern collapse during the subsequent photolithography development step .
[Medium] Dielectric Constant (k-value) Degradation: If the cleaning chemistry contains penetrative organic solvents or if process temperatures are too high, the solution can ingress into the micro-pores of the underlying dielectric layers . This introduces polar functional groups and moisture, which significantly raises the local dielectric constant and degrades device switching speeds .
[Medium] Nanoparticle-Induced Via Blockage: Suboptimal megasonic power limits the generation of effective cavitation microjets, preventing the physical detachment of nanoscale particles from the ILD surface . These remaining particles act as opaque micromasks during the Via 3 UV exposure, resulting in unexposed regions that fail to clear during development and ultimately cause open-circuit vias (Engineering Practice).
[Low] Dielectric Surface Pitting: Excessive megasonic power or the use of an unbalanced cleaning formulation lacking proper surface-adsorption inhibitors can lead to localized chemical or mechanical attack on the ILD 3-2 oxide . This increases surface roughness and thickness variation, which negatively impacts the depth-of-focus margin during the high-resolution Via 3 lithography step .

The Pre Litho Cleaning step in the ILD3 module is critically posi

[High] Photoresist Adhesion Failure: Incomplete oxidation and removal of organic contaminants due to insufficient ozone concentration or gas-liquid contact time leaves hydrophobic residues on the dielectric . This localized low surface energy prevents proper BARC wetting, leading to resist peeling or pattern collapse during the subsequent photolithography development step .
[Medium] Dielectric Constant (k-value) Degradation: If the cleaning chemistry contains penetrative organic solvents or if process temperatures are too high, the solution can ingress into the micro-pores of the underlying dielectric layers . This introduces polar functional groups and moisture, which significantly raises the local dielectric constant and degrades device switching speeds .
[Medium] Nanoparticle-Induced Via Blockage: Suboptimal megasonic power limits the generation of effective cavitation microjets, preventing the physical detachment of nanoscale particles from the ILD surface . These remaining particles act as opaque micromasks during the Via 3 UV exposure, resulting in unexposed regions that fail to clear during development and ultimately cause open-circuit vias (Engineering Practice).
[Low] Dielectric Surface Pitting: Excessive megasonic power or the use of an unbalanced cleaning formulation lacking proper surface-adsorption inhibitors can lead to localized chemical or mechanical attack on the ILD 3-2 oxide . This increases surface roughness and thickness variation, which negatively impacts the depth-of-focus margin during the high-resolution Via 3 lithography step .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

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In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges