ILD 3-2 Deposition - 40nm

Extended surface diffusion times enable the precursors to accommodate underlying topology before final network crosslinking, thereby ensuring excellent step coverage and uniform film thickness .

The ILD 3-2 Deposition step forms the upper inter-metal dielectric layer for the Metal 3 / Via 3 (M3/V

interconnect level, following the foundational ILD 3-1 layer . In advanced Back-End-Of-Line (BEOL) interconnect integration, the dielectric stack is frequently divided into a first dielectric layer serving as the via dielectric (ILD 3-1) and a sequentially deposited second dielectric layer serving as the trench dielectric (ILD 3-2) . This bi-layer approach allows the subsequent Via 3 and Metal 3 trench to be patterned with independent depth control, often facilitated by an intermediate etch stop layer . Unlike the earlier ILD 1-2 Deposition step, which is located closer to the active devices and faces the most aggressive capacitance constraints, ILD 3-2 resides higher in the interconnect hierarchy where mechanical robustness for subsequent Chemical Mechanical Planarization (CMP) and global routing layout rules take greater precedence . This step prepares the physical volume that will be selectively removed during the subsequent ILD 3-2 Oxide Etch to house the metallic routing lines (Engineering Practice). The physical deposition of this dielectric layer typically relies on Plasma-Enhanced Chemical Vapor Deposition (PECVD) utilizing precursors such as tetraethoxysilane (TEOS) or organosilicate species to form a crosslinked silicon dioxide or carbon-doped oxide (SiCOH) network . During this process, reactive oxygen or nitrogen radicals generated in the plasma interact with the surface-adsorbed precursor molecules . Film growth is fundamentally governed by a balance of surface diffusion and secondary condensation reactions rather than strictly bulk gas-phase decomposition . Precursor molecules undergo partial cleavage of their Si–O bonds, yielding highly mobile surface species that migrate across the substrate to form stable chain-like structures and a final dense network . Extended surface diffusion times enable the precursors to accommodate underlying topology before final network crosslinking, thereby ensuring excellent step coverage and uniform film thickness . Material selection for ILD 3-2 demands a careful compromise between minimizing the dielectric constant (k-value) to reduce interconnect RC delay and maintaining sufficient mechanical and electrical integrity . Carbon-doped SiCOH films are commonly utilized because incorporating porosity and lighter organic groups lowers the material's polarizability, meeting the capacitance targets for advanced VLSI circuits . However, scaling the interconnect layout rules inherently reduces metal spacing, which concentrates thermo-mechanical stress and drastically increases local electric fields . Consequently, process parameters such as deposition temperature, RF plasma power, and precursor flow ratios must be precisely modulated; for example, increasing the deposition temperature tends to decrease the surface precursor concentration, shifting the condensation reaction into a kinetically limited regime that extends the effective diffusion mean free path . If the plasma conditions are overly aggressive, energetic ion bombardment can inadvertently break Si–C bonds and induce structural rearrangement, undermining the film's intended dielectric properties . For a nanoscale Back-Side Illuminated (BSI) CMOS Image Sensor, the scaling of the BEOL structural dimensions approaches physical limits where Time-Dependent Dielectric Breakdown (TDDB) becomes a dominant failure mechanism . Under continuous electrical bias, energetic carriers can tunnel into the dielectric film, creating localized defects that accumulate until a critical density triggers catastrophic structural breakdown . Furthermore, because the BEOL stack in a BSI sensor acts as the mechanical foundation during subsequent aggressive wafer thinning and carrier bonding processes, the ILD 3-2 layer must withstand significant external mechanical stresses without delaminating or cracking . Therefore, the deposition parameters are optimized to maximize the cross-linking density of the dielectric matrix while strictly controlling the incorporation of hygroscopic silanol (Si–OH) groups that could otherwise compromise long-term device reliability .

[High] Time-Dependent Dielectric Breakdown (TDDB): Under the intense local electric fields present in scaled nanoscale BEOL metal spacings, energetic charge carriers tunnel into the dielectric film and generate structural defects . Over time, these defects accumulate to a critical threshold, ultimately creating a conductive path that causes catastrophic breakdown and shorts adjacent metal lines .
[High] Dielectric Constant (k-value) Degradation: Exposure of the porous SiCOH dielectric to reactive plasma environments causes highly reactive radicals to chemically attack Si-C bonds and deplete carbon from the surface . This triggers localized structural rearrangement and pore collapse, generating a densified layer that readily absorbs moisture and drastically increases the effective dielectric constant .
[Medium] Sub-surface Voiding: If the deposition temperature is lowered or precursor flow rates are excessively high, the surface mobility of the film-forming precursor intermediates is outpaced by the rapid condensation reaction rate . This restricted diffusion mean free path causes geometrical shadowing over micro-topologies, physically trapping voids within the bulk of the dielectric film .
[Low] Misalignment and Etch Stop Layer Penetration: Variations in the deposited thickness or film density of the ILD 3-2 trench dielectric layer alter its localized plasma etch rate during the subsequent damascene trench etching . If the etch rate fluctuates unexpectedly, the etch process may punch through the underlying etch stop layer, destroying the self-aligned boundary and damaging the ILD 3-1 via structures .

Extended surface diffusion times enable the precursors to accommodate underlying topology before final network crosslinking, thereby ensuring excellent step coverage and uniform film thickness .

The ILD 3-2 Deposition step forms the upper inter-metal dielectric layer for the Metal 3 / Via 3 (M3/V

interconnect level, following the foundational ILD 3-1 layer . In advanced Back-End-Of-Line (BEOL) interconnect integration, the dielectric stack is frequently divided into a first dielectric layer serving as the via dielectric (ILD 3-1) and a sequentially deposited second dielectric layer serving as the trench dielectric (ILD 3-2) . This bi-layer approach allows the subsequent Via 3 and Metal 3 trench to be patterned with independent depth control, often facilitated by an intermediate etch stop layer . Unlike the earlier ILD 1-2 Deposition step, which is located closer to the active devices and faces the most aggressive capacitance constraints, ILD 3-2 resides higher in the interconnect hierarchy where mechanical robustness for subsequent Chemical Mechanical Planarization (CMP) and global routing layout rules take greater precedence . This step prepares the physical volume that will be selectively removed during the subsequent ILD 3-2 Oxide Etch to house the metallic routing lines (Engineering Practice). The physical deposition of this dielectric layer typically relies on Plasma-Enhanced Chemical Vapor Deposition (PECVD) utilizing precursors such as tetraethoxysilane (TEOS) or organosilicate species to form a crosslinked silicon dioxide or carbon-doped oxide (SiCOH) network . During this process, reactive oxygen or nitrogen radicals generated in the plasma interact with the surface-adsorbed precursor molecules . Film growth is fundamentally governed by a balance of surface diffusion and secondary condensation reactions rather than strictly bulk gas-phase decomposition . Precursor molecules undergo partial cleavage of their Si–O bonds, yielding highly mobile surface species that migrate across the substrate to form stable chain-like structures and a final dense network . Extended surface diffusion times enable the precursors to accommodate underlying topology before final network crosslinking, thereby ensuring excellent step coverage and uniform film thickness . Material selection for ILD 3-2 demands a careful compromise between minimizing the dielectric constant (k-value) to reduce interconnect RC delay and maintaining sufficient mechanical and electrical integrity . Carbon-doped SiCOH films are commonly utilized because incorporating porosity and lighter organic groups lowers the material's polarizability, meeting the capacitance targets for advanced VLSI circuits . However, scaling the interconnect layout rules inherently reduces metal spacing, which concentrates thermo-mechanical stress and drastically increases local electric fields . Consequently, process parameters such as deposition temperature, RF plasma power, and precursor flow ratios must be precisely modulated; for example, increasing the deposition temperature tends to decrease the surface precursor concentration, shifting the condensation reaction into a kinetically limited regime that extends the effective diffusion mean free path . If the plasma conditions are overly aggressive, energetic ion bombardment can inadvertently break Si–C bonds and induce structural rearrangement, undermining the film's intended dielectric properties . For a nanoscale Back-Side Illuminated (BSI) CMOS Image Sensor, the scaling of the BEOL structural dimensions approaches physical limits where Time-Dependent Dielectric Breakdown (TDDB) becomes a dominant failure mechanism . Under continuous electrical bias, energetic carriers can tunnel into the dielectric film, creating localized defects that accumulate until a critical density triggers catastrophic structural breakdown . Furthermore, because the BEOL stack in a BSI sensor acts as the mechanical foundation during subsequent aggressive wafer thinning and carrier bonding processes, the ILD 3-2 layer must withstand significant external mechanical stresses without delaminating or cracking . Therefore, the deposition parameters are optimized to maximize the cross-linking density of the dielectric matrix while strictly controlling the incorporation of hygroscopic silanol (Si–OH) groups that could otherwise compromise long-term device reliability .

[High] Time-Dependent Dielectric Breakdown (TDDB): Under the intense local electric fields present in scaled nanoscale BEOL metal spacings, energetic charge carriers tunnel into the dielectric film and generate structural defects . Over time, these defects accumulate to a critical threshold, ultimately creating a conductive path that causes catastrophic breakdown and shorts adjacent metal lines .
[High] Dielectric Constant (k-value) Degradation: Exposure of the porous SiCOH dielectric to reactive plasma environments causes highly reactive radicals to chemically attack Si-C bonds and deplete carbon from the surface . This triggers localized structural rearrangement and pore collapse, generating a densified layer that readily absorbs moisture and drastically increases the effective dielectric constant .
[Medium] Sub-surface Voiding: If the deposition temperature is lowered or precursor flow rates are excessively high, the surface mobility of the film-forming precursor intermediates is outpaced by the rapid condensation reaction rate . This restricted diffusion mean free path causes geometrical shadowing over micro-topologies, physically trapping voids within the bulk of the dielectric film .
[Low] Misalignment and Etch Stop Layer Penetration: Variations in the deposited thickness or film density of the ILD 3-2 trench dielectric layer alter its localized plasma etch rate during the subsequent damascene trench etching . If the etch rate fluctuates unexpectedly, the etch process may punch through the underlying etch stop layer, destroying the self-aligned boundary and damaging the ILD 3-1 via structures .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges