In the backend-of-line (BEOL) process flow for a 40nm BSI CMOS Image Sensor, the Via 3 Lithography (VIA 3 - Photo) step serves as the critical pattern-definition stage immediately following the deposition of the ILD 3-2 and ILD 3-1 dielectric layers T1.The fundamental objective of this step is to spatially define the vertical interconnects (vias) that will electrically bridge the underlying Metal 3 routing to the future Metal 4 layer A1.The applied photoresist layer acts as a sacrificial templat