40nm BSI CMOS Image SensorPreview

[P2]. Before transitioning to the Shallow Trench Isolation (STI) module, which begins with the deposition of a silicon nitride (SiN) and silicon oxide (SiO) hard mask stack, the silicon surface must be absolutely pristine [P2]. Any residual contaminants, such as metallic impurities, organic residues, or uncontrolled native oxides left from previous wet etch steps, can degrade the quality of the subsequent hard mask interfaces and introduce defects [T1]. Therefore, this Pre-Cleaning step serves as the critical bridge between DTI completion and STI initiation, ensuring uniform surface conditions for the upcoming deposition processes (Engineering Practice). The core physical and chemical mechanism of this wet pre-cleaning process involves the controlled oxidation of the silicon surface followed by the isotropic dissolution of that newly formed oxide, which effectively undercuts and lifts off surface particles and contaminants [P1]. Oxidizing agents in the chemical bath react with the bare silicon to form an ultrathin, self-limiting chemical oxide layer [P1]. In conjunction with or subsequent to this oxidation, a dilute etchant strips the chemical oxide, carrying away trace metals and trapped particulate matter (Engineering Practice). This cyclical or balanced oxidation-dissolution mechanism ensures that the silicon surface is renewed without inducing excessive topographical damage [P1]. Maintaining an atomically smooth surface is targeted during these steps because surface roughness degrades carrier mobility in scaled channel materials [P1]. Furthermore, effectively minimizing bulk and interface-trap densities at this stage is necessary to prevent parasitic leakage paths and improve overall device reproducibility [T1]. Wet chemical cleaning is selected over dry plasma cleaning for this step because it provides highly isotropic, damage-free removal of surface contaminants without introducing plasma-induced lattice defects or charging effects [P1]. The process parameters, such as chemical concentration, bath temperature, and exposure time, must be tightly controlled to balance the oxidation rate driven by oxidants against the dissolution kinetics [P1]. If the etchant concentration is excessively high, it can lead to localized over-etching at crystal defects or uneven removal of the existing DTI dielectric fill material [A2]. Conversely, insufficient oxidant concentration fails to completely passivate the surface and lift off metallic contaminants, leaving behind recombination centers that severely degrade device performance [T1]. Additionally, the final chemical termination of the silicon surface (typically hydrogen-terminated) is engineered to prevent immediate re-oxidation in ambient air before the wafer enters the vacuum chamber for SiN hard mask deposition [A2]. In nanoscale Backside Illuminated (BSI) CMOS Image Sensors, precise surface state control and minimal defect density are paramount to suppressing dark current and white pixel defects [P2]. Because the active pixel regions are highly sensitive to any electrical noise generated by interface traps, the pre-cleaning step must achieve sub-nanometer etch control to prevent active area loss or defect nucleation [P1]. The combined presence of completed DTI structures and the impending STI trench formation means that the cleaning chemistry must be highly selective; it must ensure that the previously filled DTI dielectric is not excessively recessed while the silicon active area is perfectly prepared for the STI hard mask [P3].