The process parameters—such as etchant concentration, temperature, and radical flux—must be tightly controlled to balance the removal rate against the risk of over-etching .
The Oxide Hard Mask Removal step is strategically positioned after the planarization and wet etch clearance of the excess D
eep Trench Isolation (DTI) SiN fill . At this stage in the flow, the oxide hard mask—which previously served as the robust template for high-aspect-ratio Deep Reactive Ion Etching (DRIE) of the silicon trenches—has fulfilled its structural purpose . Leaving this thick oxide layer in place would disrupt the topographical baseline required for the subsequent shallow trench isolation (STI) module, which relies on the deposition of a new, pristine SiN/SiO hard mask stack . By completely stripping this sacrificial oxide, the process resets the wafer surface, exposing the active silicon (or a thin pad oxide) to ensure proper adhesion and uniform thickness for the downstream SiN Hard Mask Deposition . This step is fundamentally distinct from the later Oxide Hard Mask Etch, as it represents a blanket isotropic strip rather than an anisotropic pattern-transfer operation (Engineering Practice). The physical and chemical mechanism for this removal relies on highly selective isotropic etching, most commonly utilizing hydrofluoric acid (HF) based wet chemistries . Fluorine-based aqueous solutions react with the silicon dioxide matrix to form volatile or water-soluble byproducts, achieving virtually complete selectivity over the adjacent bare silicon and the newly planarized SiN DTI fill . Alternatively, chemical downstream etching or remote plasma processes can be utilized, where neutral fluorine radicals chemically reduce the oxide without the physical sputtering associated with direct ion bombardment . When dry plasma techniques are employed, introducing hydrogen radicals acts as a passivating agent that transiently protects the adjacent silicon nitride surfaces, thereby enhancing the overall etch selectivity and preventing unintended material loss . The choice of highly selective wet HF etching or carefully modulated downstream plasma is driven by the necessity to avoid physical damage to the active silicon surface and the trench structures . Direct capacitively coupled plasma etching is generally avoided here, as high-energy ion bombardment would induce surface amorphization and non-selective physical sputtering . The process parameters—such as etchant concentration, temperature, and radical flux—must be tightly controlled to balance the removal rate against the risk of over-etching . Insufficient processing leaves microscopic oxide residues, while excessive exposure risks attacking the structural trench liner oxide, potentially leading to structural pinch-off or tapering of the adjacent isolation spacers . At the 40nm node for Backside Illuminated (BSI) CMOS Image Sensors, preserving the crystalline integrity of the active area and the DTI boundaries is critical . Any surface roughness or physical damage introduced during this strip creates interface trap states that act as Shockley-Read-Hall (SRH) recombination centers . These defects locally reduce photogenerated carrier lifetimes and manifest as severe dark current or white pixel defects in the final sensor array . Furthermore, uniform mask removal prevents localized mechanical stress gradients from transferring into the active channel, which would otherwise modulate carrier mobility and degrade transistor subthreshold characteristics .
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