The Oxide Hard Mask Etch is a critical pattern transfer step that directly follows photolithography and precedes the highly demanding silicon deep trench etch .Its primary function is to transfer the critical dimensions defined by the photoresist into the underlying SiO2 layer, creating a robust hard mask for the subsequent Deep Trench Isolation (DTI) formation .A dedicated hard mask is strictly necessary because the subsequent silicon Deep Reactive-Ion Etch (DRIE) requires achieving extremely high aspect ratios, up to 20 or more .During such prolonged and aggressive silicon etching, conventional polymeric photoresists undergo rapid erosion, causing severe selectivity degradation and profile distortion .Unlike a generic "Oxide Etch" which might simply clear a contact hole, or "SiO Hard Mask Deposition" which merely forms the blanket film, this specific step defines the spatial boundaries of the DTI that will ultimately suppress electrical and optical crosstalk between pixels .The etching of the SiO2 hard mask relies on a high-density inductively coupled plasma (ICP) utilizing fluorocarbon-based chemistries .The fundamental etching mechanism is a synergistic physical-chemical process where energetic ions bombard the surface to break Si-O bonds, allowing fluorine radicals to react and form volatile effluents such as SiFx and COx .Concurrently, fluorocarbon radicals (CFx) polymerize on the etched surfaces, depositing a carbon-rich passivation layer .Anisotropic pattern transfer is achieved because directional ion acceleration, driven by the applied bias voltage, preferentially removes this polymer from the horizontal bottom surfaces while the vertical sidewalls remain protected .To maintain high selectivity to the overlying photoresist, the carbon-to-fluorine (C/F) ratio of the plasma is carefully modulated, often through the introduction of CH4 or H2, which enhances the polymer formation rate on non-oxide surfaces .The selection of SiO2 as the DTI hard mask is driven by its exceptional etch resistance against the aggressive fluorine or sulfur hexafluoride (SF6) plasmas typically used in subsequent silicon Bosch processes .During the oxide etch itself, key control parameters include gas composition, chamber pressure, and gas residence time .Residence time serves as a core tuning knob; modifying the gas flow rates and pumping speeds directly affects radical dissociation efficiency and the delicate balance between polymerization and etching .Furthermore, as device features shrink, the lithographically printed resist lines are often trimmed via isotropic etching techniques prior to the hard mask etch to achieve sub-lithographic dimensions .The precise control of the oxide hard mask's sidewall angle is essential, as any tapering or bowing will transfer into the silicon substrate, potentially damaging adjacent active regions and compromising device isolation .For a 40nm BSI CMOS Image Sensor, pixel dimensions are tightly scaled, requiring the DTI to be both exceptionally deep and narrow to maximize the photodiode fill factor .The structural fidelity of the oxide hard mask dictates the final volume of the DTI, which in turn influences the Si/SiO2 interface area where Shockley-Read-Hall (SRH) recombination occurs .If the hard mask etch introduces excessive critical dimension (CD) loss or surface roughness, the resulting DTI sidewalls may exhibit higher defect densities, thereby degrading the photodiode's responsivity and introducing non-linear optical responses under varying incident fluxes .
Impact of Trap States at Deep Trench Sidewalls on the Responsivity of Island Photodiodes
2023
A Shallow and Deep Trench Isolation Process Module for RF BiCMOS
2004
Selective and deep plasma etching of SiO2: Comparison between different fluorocarbon gases (CF4, C2F6, CHF3) mixed with CH4 or H2 and influence of the residence time
2002
DREM: Infinite etch selectivity and optimized scallop size distribution with conventional photoresists in an adapted multiplexed Bosch DRIE process
2018
Physics of Semiconductor Devices - Full
2006
Modern Semiconductor Devices for Integrated Circuits - MOSFETs in ICs
2010
Semiconductor device structure and methods of forming the same
2023
Method for making a high aspect ratio trench
2024
Questions about this step? Ask AI
AI process assistant backed by 10,000+ papers & patents