40nm BSI CMOS Image Sensor

In the F_DTI (Frontside Deep Trench Isolation) module of a 40nm BSI CMOS Image Sensor, deep trenches are required to optically and electrically isolate pixels, thereby reducing crosstalk [P1].To etch trenches with aspect ratios exceeding 20:1 into the silicon epitaxial layer, standard photoresist masks are rapidly consumed and thus physically insufficient [P1].Therefore, a robust intermediate layer is required, which is the primary purpose of this SiO hard mask deposition step [A1].This step follows general wafer-level ashing and cleaning to ensure a pristine surface, and it prepares the wafer for subsequent lithography and oxide etching to pattern the mask itself [P2].Unlike shallow trench isolation (STI) hard masks which typically rely on a pad oxide and a thicker silicon nitride stack to act as a chemical-mechanical polishing (CMP) stop [P2], this specific SiO layer acts solely as a sacrificial physical barrier during the highly aggressive deep reactive-ion etch (DRIE) of the bulk silicon [P1].Plasma-Enhanced Chemical Vapor Deposition (PECVD) or similar CVD methods are typically employed to deposit this thick oxide layer at relatively low thermal budgets [P2].Precursor gases react in a plasma environment to form amorphous SiO2 networks on the wafer surface [A1].The plasma provides the essential activation energy for the chemical reaction, allowing deposition at temperatures well below those required for conventional thermal oxidation (Engineering Practice).The resulting film must be extremely dense and uniform to prevent localized micro-masking or uneven erosion during the subsequent silicon deep etch [P2].Erosion of the hard mask during DRIE can lead to microtrenching or widening of the trench top, which adversely affects the final deep trench profile and overall device reliability [P2].Silicon dioxide is selected over silicon nitride or metal hard masks because it offers excellent etch selectivity to silicon during the aggressive fluorine or bromine-based chemistries utilized in deep silicon etching [P2].During DRIE, the etch rate of silicon is substantially higher than that of the SiO2 hard mask, allowing a moderately thick oxide to protect the active areas throughout the prolonged deep etch process [P1].Parameters such as deposition temperature, RF power, and precursor gas ratios directly interact to determine the film's internal stress, density, and deposition rate (Engineering Practice).If the film stress is excessively compressive or tensile, it can cause severe wafer bowing or catastrophic film delamination before or during the deep trench etch [P3].Therefore, the deposition parameters are strictly monitored to balance high manufacturing throughput with sufficient film density to minimize the mask erosion rate [P2].For a 40nm BSI CMOS image sensor, the pixel pitch is extremely small, demanding highly precise control over the DTI lateral dimensions to maximize the active photodiode volume [P1].Because the DTI sidewalls act as Shockley-Read-Hall (SRH) recombination centers that can nonlinearly affect photodiode responsivity, the trench profile must be perfectly vertical without any top-edge faceting [P1].A thicker, high-quality SiO hard mask mitigates the risk of mask faceting transferring into the underlying silicon, ensuring that the trench maintains its designed critical dimension (CD) from top to bottom [P2].This geometric fidelity is essential because any variation in trench width directly impacts the quantum efficiency and crosstalk isolation of the sub-micron pixels [P1].

• [High] Hard Mask Erosion and Faceting: During the prolonged deep reactive-ion etching (DRIE), the corners of the hard mask can erode faster than the flat surfaces, leading to severe faceting [P2].If the mask is insufficiently thick or its density is too low, this faceting reaches the silicon substrate, causing trench top widening and microtrenching that reduces the active area of the photodiode [P1].- [Medium] Excessive Film Stress Leading to Delamination: Thick PECVD oxide films can accumulate significant internal stress depending on the RF power and deposition temperature applied [P3].High stress levels can cause the hard mask to crack, induce wafer bowing, or delaminate from the underlying substrate, leading to catastrophic masking failures during the subsequent DRIE step [P3].- [Medium] Particulate Generation and Micro-masking: Incomplete gas-phase reactions or flaking from the CVD chamber walls can deposit particles on the wafer surface during the SiO deposition process [A1].These particles act as localized physical masks during the subsequent oxide hard mask etch, eventually transferring needle-like silicon defects into the deep trench [P2].- [Low] Non-uniform Film Thickness: Variations in plasma density or precursor flow across the wafer can result in center-to-edge thickness non-uniformity of the deposited oxide [A1].While a certain degree of over-thickness is tolerated, severe non-uniformity can cause the mask to clear prematurely at the wafer edges during the deep trench etch, exposing active silicon regions to irreversible plasma damage [P2].