40nm BSI CMOS Image SensorFree after sign-in

In the 40nm BSI CMOS Image Sensor integration flow, this specific Pre Litho Cleaning step is executed immediately following SiO hard mask deposition and prior to Frontside Deep Trench Isolation (DTI) photolithography [P3]. Unlike other routine pre-litho cleans that prepare planar dielectric or silicon surfaces throughout the flow, this step uniquely prepares a thick, newly deposited SiO hard mask for a critical high-aspect-ratio patterning step [P3]. The subsequent DTI photo process requires pristine adhesion of a thick photoresist layer to withstand the aggressive and prolonged anisotropic silicon full trench etching [P3]. Any particulate contamination or organic residue on the hard mask surface will perturb the photoresist spin-coating process, leading to coating striations and localized defocus during photolithography [A1]. Therefore, this cleaning step ensures a defect-free, chemically uniform surface to maximize pattern fidelity and alignment tolerance for the deep trench structures [A1]. The physical and chemical mechanisms of this wet clean revolve around the oxidative degradation of organic contaminants and the electrostatic repulsion of particulates [P2]. Solutions such as the Sulfuric Peroxide Mixture (SPM, H2SO4/H2O2) rely on strong oxidative reactions to efficiently decompose adventitious organics while virtually not etching the underlying SiO2 hard mask [P2]. Preserving the surface planarity of the SiO layer is critical because chemical etching of SiO2 by hydroxyl ions (OH-), which occurs in standard alkaline cleans like APM or SC1, can induce severe surface micro-roughness [P2]. This micro-roughness alters the local surface energy, compromising the uniform wetting of the photoresist solvent during the subsequent spin-coating process [A1]. Furthermore, if standard cleans like SC1 (ammonium hydroxide and hydrogen peroxide) or SC2 (hydrochloric acid and hydrogen peroxide) are employed for trace particle and metal removal, their concentrations must be strictly controlled to balance cleaning efficiency against dielectric surface degradation [A1]. The selection of the specific chemical suite is governed by the need to balance contaminant removal with the structural and dimensional integrity of the SiO hard mask [P2]. SPM is frequently favored over APM in this module because SPM's low etch rate characteristics preserve the hard mask's thickness, which is a critical parameter for surviving the subsequent long-duration DTI reactive ion etching [P2]. Process parameters such as cleaning temperature, chemical residence time, and mixture ratios directly determine the organic removal efficiency and the extent of oxide damage [P2]. Higher temperatures accelerate the kinetic rate of organic oxidation but also increase the risk of peroxide decomposition, necessitating precise bath life management [P2]. Additionally, the final rinse and drying processes must be optimized to prevent water mark formation, which act as unwanted micro-masking defects during the photolithography exposure [A1]. In the specific context of 40nm BSI CIS technology, the DTI structures serve as fundamental optical and electrical isolation barriers between adjacent sub-micron pixels [P3]. High-fidelity patterning is absolutely essential, as any line-edge roughness (LER) initiated by poor pre-litho cleaning will be transferred through the hard mask and amplified during the deep trench etch [P3]. This geometric amplification creates striated trench sidewalls that can severely degrade the sensor's performance by inducing unwanted optical scattering and trap-assisted dark current generation at the silicon-dielectric interface [T1]. Thus, stringent control over the hard mask surface state via this tailored pre-litho clean is a prerequisite for achieving the high-performance vertical isolation required in advanced image sensors [P3].