40nm BSI CMOS Image Sensor

The CMP Removal of Excess Nitride step is strategically positioned immediately following the Deep Trench Isolation (DTI) SiN Fill to achieve global planarization of the wafer surface [P2].To ensure a void-free fill of the extreme aspect ratio trenches, the preceding deposition inherently leaves a thick, uneven SiN overburden across the wafer [A2].Chemical Mechanical Planarization (CMP) is the only viable technology capable of robustly eliminating this topographic overburden to ensure flatness for subsequent photolithography and layer deposition steps [P2, A2].This step is functionally distinct from the downstream Wet Etch Removal of Excess Nitride: the CMP step performs bulk, anisotropic mechanical planarization to level the surface, whereas the subsequent wet etch provides highly selective, isotropic clearing of the final residual SiN without damaging the underlying oxide hard mask [P2].Furthermore, it differs from the Nitride Hard Mask Removal module, as this specific operation targets the structural gap-fill dielectric within the trenches rather than the sacrificial masking layers used for active area definition [P2].The physical removal mechanism is governed by the synergistic coupling of chemical surface modification and mechanical abrasion [P1].According to Preston's equation, the material removal rate is directly proportional to the applied mechanical pressure and the relative velocity between the wafer and the polishing pad [P3, A1].In this specific operation, the slurry chemistry must actively promote the surface hydrolysis of the SiN overburden, converting the highly crosslinked nitride into a softer, oxidized layer that is easily sheared away by moving abrasive particles [P1].Unlike standard Shallow Trench Isolation (STI) CMP where silicon nitride acts as a protected polish-stop layer via the strategic adsorption of specific amino acids [P1], this step requires a slurry dynamically tuned for a high SiN removal rate [A1].By utilizing precisely engineered polyhydroxy nonionic organic molecules alongside targeted chemical additives, the hydration layer thickness and interfacial friction on the target films can be modulated, ensuring an aggressive yet controlled removal of the bulk nitride [A1].Material selection for the CMP consumables fundamentally dictates process stability, removal selectivity, and defectivity [P2].Ceria (CeO2) coated abrasives are frequently utilized because their surfaces exhibit variable valence states (Ce3+/Ce4+) that form strong, reversible chemical bonds with oxidized silicon interfaces, heavily enhancing the chemically assisted mechanical removal mechanism [P2, P4].To uniformly distribute these highly reactive abrasives and manage localized mechanical stress, microstructure polishing pads featuring regular, uniform micro-channels and micro-protrusions are employed [P3].These engineered pad structures alter the fluid dynamics and contact mechanics, effectively stabilizing the pressure distribution and improving slurry renewal efficiency at the pad-wafer interface [P3].Consequently, the microstructure pad significantly suppresses pattern-dependent erosion and limits step height variations across wide and narrow active area arrays [P3, P4].At the 40nm node, Back-Side Illuminated (BSI) CMOS Image Sensors feature exceedingly dense pixel pitches, making the structural integrity of the DTI highly sensitive to nanoscale topography variations [T1].Over-polishing or non-uniform removal would prematurely expose the underlying oxide hard mask, threatening the pristine nature of the active silicon surface where the critical MOSFET inversion layer will later form [T1].Because carrier surface mobility is strictly limited by interface scattering and surface perpendicular electric fields [T1], maintaining a uniform oxide buffer is essential to prevent degradation of the transistor's drive current [T1].Therefore, achieving decoupled, highly tunable removal rates between the SiN fill and the underlying oxide layer via advanced slurry chemistry is a mandatory requirement for sub-50nm planarization consistency [A1].

• [High] Dishing and Erosion of DTI Fill: If overpolishing occurs or if the polishing pad conforms too deeply into the trench arrays, the SiN fill inside the DTI structures is excessively removed [P4].This localized erosion creates step height variations and compromises the physical barrier between adjacent active elements [A2].Consequently, electrical isolation is weakened, leading to increased crosstalk and severe noise degradation in the image sensor array (Engineering Practice).- [Medium] Incomplete Bulk Overburden Planarization: Inadequate mechanical pressure, suboptimal relative velocity, or localized slurry starvation at the pad interface can lead to incomplete planarization [P3].This leaves significant residual step heights across varying pattern densities, forcing the subsequent highly selective wet etch step to process an uneven starting thickness (Engineering Practice).If the wet etch cannot clear this nonuniform residue, residual material will remain and interfere with the structural integrity of subsequent layer depositions [P2].- [Medium] Micro-scratching from Agglomerated Abrasives: The ceria-based high selectivity slurries used to achieve precise chemical planarization are prone to abrasive particle agglomeration if filtration is inadequate [P4].These large agglomerates generate intense, localized mechanical shear forces that cause deep micro-scratches on the wafer surface [P4].If these scratches penetrate the oxide hard mask and enter the active silicon substrate, they introduce trap states that disrupt the crystalline periodic potential, thereby severely increasing leakage currents [T2].- [Low] Premature Breakthrough to Active Silicon: If the slurry's chemical selectivity fails or process time is significantly exceeded, the CMP operation may entirely consume the protective oxide hard mask and mechanically damage the underlying active silicon [P2].Because a MOSFET's drain-source current is inherently determined by the inversion charge and electron surface mobility [T1], any mechanical disruption to the silicon surface will drastically increase surface scattering and irrevocably degrade device transconductance [T1].