40nm BSI CMOS Image Sensor

The Frontside Deep Trench Isolation (F_DTI) Photo step is a critical lithographic process in 40nm Backside Illuminated (BSI) CMOS Image Sensors, responsible for defining the deep isolation grid between adjacent photodiode pixels [P1].Unlike Shallow Trench Isolation (STI) photo, which defines shallow active area boundaries to prevent surface leakage [P3], or metal trench photos that pattern back-end dielectric interconnects [T1], the F_DTI photo prepares the wafer for a high-aspect-ratio vertical etch that penetrates deep into the epitaxial silicon [P1].This step follows the deposition of a thick SiO hard mask [P1].Because the subsequent deep reactive-ion etch (DRIE) of silicon requires a robust masking material to achieve aspect ratios up to 20, the photoresist pattern is strictly used to etch this intermediate oxide hard mask [P1].By precisely defining this boundary, the process establishes the physical structure needed to block lateral minority carrier diffusion, thereby suppressing electrical and optical crosstalk between miniature pixels [P1].The core mechanism of this step relies on optical lithography to transfer the DTI geometric pattern from a photomask into a photosensitive polymer layer [T1].The resolution of this pattern transfer is governed by the Rayleigh criterion, where the minimum resolvable feature size depends on the exposure wavelength and the numerical aperture of the lens system [T1].In advanced nodes, step-and-repeat projection systems are employed to expose small lithography fields sequentially, minimizing the impact of lens distortion [T1].During exposure, light induces a photochemical reaction within the resist, altering its solubility in a developer solution to form the trench openings [P1].To combat the severe diffraction effects at 40nm design rules, mathematical Optical Proximity Correction (OPC) is applied to the mask layout [T1].OPC modifies the shapes of the trench line-ends and intersections to compensate for the proximity effect of neighboring light and dark patterns, ensuring the developed trench network is continuous and sharp [T2].Material selection for this photo step typically involves a multi-layer resist system, including a bottom anti-reflective coating (BARC) to suppress standing waves generated by light reflection from the highly reflective underlying hard mask (Engineering Practice).The resist thickness must be carefully optimized; it must be thin enough to prevent pattern collapse under high capillary forces during development, yet thick enough to withstand the subsequent oxide hard mask open etch [P3].Furthermore, process engineers must balance the trade-off between exposure dose and depth of focus (DOF) [T1].A higher numerical aperture improves line-width resolution but significantly shrinks the available DOF, making the process highly sensitive to any underlying wafer topography or planarization imperfections [T1].Precise control of the focus-exposure matrix is required to achieve strictly vertical resist sidewalls, as any slope in the resist profile will linearly transfer into the hard mask and compromise the anisotropy of the final silicon deep trench [P2].In the specific context of 40nm image sensors, where pixel pitches are scaled to approximately 1 µm or below, controlling the lithographic line-edge roughness (LER) is of paramount importance [P1].If the photoresist exhibits excessive waviness—often caused by the graininess of the polymer matrix or imperfect post-exposure bake conditions [T2]—this roughness will propagate down the trench sidewalls during the DRIE process [P1].Rough deep trench sidewalls dramatically increase the surface area of the Si/SiO₂ interface, introducing a higher density of trap states that act as Shockley-Read-Hall (SRH) recombination centers [P1].These trap states capture and recombine photogenerated minority carriers, which fundamentally degrades the spectral response and induces a non-linear responsivity in the photodiode under high optical flux [P1].Therefore, optimizing the lithography step to produce ultra-smooth trench definitions is directly linked to the final electro-optical performance of the image sensor [P1].

• [High] Line-Edge Roughness (LER) Propagation: Random waviness in the photoresist edge caused by polymer graininess transfers directly into the hard mask and subsequently into the silicon deep trench [T2]. This physical roughness increases the Si/SiO₂ interface area, thereby introducing excess trap states that act as Shockley-Read-Hall (SRH) recombination centers and degrade photodiode responsivity [P1].
• [High] Lithographic Overlay Misalignment: Failure to perfectly align the DTI exposure field with the previously defined active area limits causes the deep trench to encroach on the functional photodiode volume [T1]. This geometric shift reduces the effective charge collection area and can introduce stress-induced leakage current near the pixel boundary [P3].
• [Medium] Focus Margin Failure (Defocus): Increasing the numerical aperture to resolve the fine DTI pitch reduces the optical depth of focus (DOF) [T1]. If local surface topography exceeds this DOF margin, the resulting resist sidewalls will be sloped rather than vertical, leading to a tapered hard mask profile and a prematurely narrowed deep trench [P2].
• [Medium] Inadequate Optical Proximity Correction (OPC): Insufficient mathematical correction of the photomask allows constructive or destructive interference between adjacent trench patterns [T1]. This can result in localized line bridging or corner rounding at the DTI grid intersections, destroying the continuous physical boundary required to block minority carrier diffusion [P1].