40nm BSI CMOS Image SensorPreview

cross-linked photoresist crust and fluorocarbon or halogen-based sidewall passivation polymers [A1]. This Ashing & Strip/Clean step is strictly required to completely remove these carbonaceous and polymeric layers before the subsequent NMOS LDD lithography and implantation [A2]. What makes this specific step unique compared to downstream back-end cleans is its immediate physical proximity to the critical gate edges and the ultra-thin gate dielectric [T1]. The exposed silicon substrate and the delicate gate stack necessitate a highly selective removal process that will not cause equivalent oxide thickness (EOT) degradation or physical recession of the source/drain silicon [P3, T1]. The physical mechanism of the ashing process relies on generating a reactive plasma to combust the organic photoresist into volatile compounds, facilitating its extraction from the wafer [A1, A3]. To mitigate plasma-induced damage at the gate dielectric corner, which can drastically increase gate-induced drain leakage (GIDL), specialized ashing chemistries such as NH3-based plasmas are often utilized instead of pure oxygen [P3]. These modified chemistries minimize the unintended oxidation of the exposed silicon and the gate stack edge, thereby preventing the formation of an undesirable "bird's beak" oxide profile [P3]. Following the dry ash, a wet strip and clean sequence is deployed to remove inorganic residues, metal contaminants, and remaining particles [A3]. This wet phase typically utilizes oxidizing and chelating agents, such as Standard Clean 1 (SC1), which operate via an oxidation-complexation-dissolution mechanism to undercut and lift off hardened polymer residues [P1, A3]. The selection of a two-step dry-then-wet method is fundamentally driven by the dual nature of the post-etch residues [P1]. The highly cross-linked resist "crust" formed during the high-energy PolySi reactive ion etch cannot be easily dissolved by wet chemicals alone, necessitating the initial oxidative plasma ash [P1]. However, pure oxygen ashing introduces severe risks of oxidizing the exposed substrate and gate sidewalls, which alters the local electric field [P3]. For the wet clean, SC1 is favored due to its robust particle removal efficiency and its ability to slightly etch the interfacial oxide to eliminate metallic contaminants [P1, A3]. Careful parameter control of the wet clean chemistry is critical; excessive etching will aggressively undercut the gate dielectric or pit the silicon substrate, leading to degraded device performance and reliability issues [P1, P3]. At the 40nm node, EOT scaling dictates the use of ultra-thin dielectrics, making them highly susceptible to quantum tunneling leakage if physically degraded or chemically altered by process variation [T1, P4]. Furthermore, the physical distance between the gate edge and the subsequent LDD implant region is minute, meaning any lateral undercut of the gate dielectric during the cleaning sequence will severely compromise short-channel control [A2]. Therefore, the balance between aggressively stripping the tough etch byproducts and preserving the delicate nanoscale structural fidelity remains the primary engineering challenge of this specific gate-level step [P1].