Pre Litho Cleaning - 40nm

The choice of wet chemical agents over dry plasma cleans is driven by the need to strictly avoid physical ion-bombardment damage to the underlying gate stack .

In the 40nm BSI CMOS Image Sensor flow, the gate module defines the critical channel-control structures of the transistors . Precedin

g this step, an As-doped polysilicon layer was deposited and subjected to a high-temperature activation anneal to set the gate work function and reduce sheet resistance . This specific Pre Litho Cleaning step prepares the annealed polysilicon surface for the subsequent Gate Formation photolithography and PolySi Etch processes . Unlike other pre-litho cleans in the flow that prepare silicon oxide or bare substrate surfaces, this step must selectively condition a heavily doped polysilicon surface without causing excessive material loss or dopant out-diffusion . Proper surface preparation is strictly required to ensure uniform photoresist coating and prevent pattern transfer defects during the critical gate definition . The high-temperature anneal typically results in the formation of a thin, uncontrolled native oxide layer on the polysilicon surface, alongside potential accumulation of organic or metallic particulate contaminants . The cleaning process utilizes a combination of oxidative and reductive chemistries to restore a pristine surface state (Engineering Practice). For instance, an ammonium hydroxide and hydrogen peroxide mixture (SC-1) removes particles and organic residues via an oxidation-complexation-dissolution mechanism, relying on electrostatic repulsion to keep particles suspended . Subsequently, a dilute hydrofluoric acid (HF) treatment, either liquid or vapor phase, strips the native oxide . HF vapor or wet cleaning yields a highly smooth, oxygen-free, and hydrophobic hydrogen-terminated surface, which thermodynamically favors the adhesion of the organic photoresist or bottom anti-reflective coating (BARC) applied in the next step . The choice of wet chemical agents over dry plasma cleans is driven by the need to strictly avoid physical ion-bombardment damage to the underlying gate stack . Furthermore, chemical concentrations and bath temperatures are precisely calibrated because heavily As-doped polysilicon exhibits a higher chemical reactivity and etch rate than undoped silicon . Over-etching the polysilicon during the clean would uncontrollably alter the gate's physical thickness and effectively shift the device's electrical characteristics . Therefore, the parameters are optimized to maximize particle removal efficiency while strictly bounding the polysilicon consumption and surface roughening . At the 40nm technology node, the control of the gate critical dimension (CD) is paramount because short-channel effects severely limit device performance . Any interfacial contamination or surface roughness generated during this clean directly translates to line-edge roughness (LER) in the photoresist pattern . Because the photoresist acts as the direct mask for the subsequent gate plasma etch, ensuring a defect-free, strongly adhered lithography interface is fundamentally required to maintain the strict gate length targets mandated by advanced CMOS physics .

[High] Photoresist Adhesion Failure: Incomplete removal of native oxide or organic residues leaves a hydrophilic surface, preventing proper bonding of the hydrophobic photoresist . This interface weakness leads to resist peeling or pattern collapse during the subsequent photolithography development step .
[High] Gate PolySi Thinning: Over-exposure to oxidative chemistries or excessively aggressive HF baths attacks the highly doped polysilicon, consuming critical gate material . This unintended material loss alters the gate sheet resistance and can degrade device performance by modifying the gate stack geometry .
[Medium] Particle Re-deposition: Incorrect chemical ratios in the cleaning bath fail to maintain a sufficient zeta potential, allowing suspended particles to re-adhere to the polysilicon . These localized particles act as micro-masks during the subsequent PolySi dry etch, causing physical gate shorts or severe line-edge roughness .
[Low] Watermark Formation: Improper drying after an HF-last step on a strongly hydrophobic silicon surface causes localized precipitation of dissolved silica as residual water droplets evaporate . These watermarks alter local optical reflectivity and resist adhesion, creating localized defects during the photolithography exposure process .

The choice of wet chemical agents over dry plasma cleans is driven by the need to strictly avoid physical ion-bombardment damage to the underlying gate stack .

In the 40nm BSI CMOS Image Sensor flow, the gate module defines the critical channel-control structures of the transistors . Precedin

[High] Photoresist Adhesion Failure: Incomplete removal of native oxide or organic residues leaves a hydrophilic surface, preventing proper bonding of the hydrophobic photoresist . This interface weakness leads to resist peeling or pattern collapse during the subsequent photolithography development step .
[High] Gate PolySi Thinning: Over-exposure to oxidative chemistries or excessively aggressive HF baths attacks the highly doped polysilicon, consuming critical gate material . This unintended material loss alters the gate sheet resistance and can degrade device performance by modifying the gate stack geometry .
[Medium] Particle Re-deposition: Incorrect chemical ratios in the cleaning bath fail to maintain a sufficient zeta potential, allowing suspended particles to re-adhere to the polysilicon . These localized particles act as micro-masks during the subsequent PolySi dry etch, causing physical gate shorts or severe line-edge roughness .
[Low] Watermark Formation: Improper drying after an HF-last step on a strongly hydrophobic silicon surface causes localized precipitation of dissolved silica as residual water droplets evaporate . These watermarks alter local optical reflectivity and resist adhesion, creating localized defects during the photolithography exposure process .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges