What is the 28nm Planar semiconductor process flow?

The 28nm Planar process flow is a semiconductor manufacturing sequence that uses a Gate-Last HKMG (High-K Metal Gate) replacement gate integration scheme. A dummy polysilicon gate is formed first, then replaced with high-k dielectric and metal gate materials after source/drain activation, enabling better threshold voltage control and lower gate leakage compared to gate-first approaches.

How many process steps are in the 28nm Planar flow?

The 28nm Planar process flow on SemiFlows contains 266 detailed process steps, covering the complete front-end-of-line (FEOL) and back-end-of-line (BEOL) integration from STI formation through metal interconnects.

What are the key modules in 28nm Planar manufacturing?

Key modules include STI (Shallow Trench Isolation), Gate formation with high-k/metal gate replacement, Spacer engineering, Source/Drain epitaxy and implant, Contact formation, and multi-level metal interconnect (M1 and above). Each module involves multiple deposition, lithography, etch, and CMP steps.

Why is gate-last preferred over gate-first at 28nm?

Gate-last (replacement metal gate) is preferred at 28nm because it avoids exposing the high-k dielectric and metal gate to high-temperature source/drain activation anneals. This preserves the work function metal properties and enables independent NMOS/PFET threshold voltage tuning, which is critical for low-power and high-performance applications.

28nm Planar Flow - 28nm Process Flow

28nm Planar Flow: Process Overview

Introduction

The 28nm planar process flow represents one of the most commercially significant nodes in the history of semiconductor manufacturing. Spanning 266 process steps across 15 distinct modules, this flow defines the last major generation of conventional bulk planar CMOS before the industry-wide transition to three-dimensional transistor architectures. At this node, the classical scaling challenges — short-channel effects, gate oxide leakage, and carrier mobility degradation — converge in ways that demand a sophisticated ensemble of process innovations while preserving the manufacturability advantages of planar topology.

The transistor architecture at 28nm remains a bulk silicon planar MOSFET, but it is substantially augmented compared to earlier nodes. Dual-gate dielectrics support both core logic and I/O voltage domains, strain engineering is applied to boost carrier mobility, and a replacement metal gate (RMG) approach eliminates the polysilicon depletion problem that fundamentally limited earlier gate stacks. The result is a device that extracts near-maximum performance from planar geometry — making 28nm a compelling long-lived node for cost-sensitive applications ranging from mobile SoCs to embedded processors.

Front-End-of-Line (FEOL)

Active Area and Isolation

The flow opens with the Active Area (AA) module, which establishes the foundational isolation framework using Shallow Trench Isolation (STI). A pad oxide and silicon nitride stack serves as a hard mask and stress buffer during trench etching. An advanced patterning stack — including an amorphous carbon film and a nitrogen-free anti-reflective coating — enables precise lithographic definition of the active area at these critical dimensions, where optical proximity effects become severe.

28nm Planar FlowPreview

28nm Planar Flow

Enter the flow from its first step

Process Overview

28nm Planar Flow: Process Overview

Introduction

Front-End-of-Line (FEOL)

Active Area and Isolation

Key integration ideas

Module Distribution

Step index

28nm Planar FlowPreview

28nm Planar Flow

Enter the flow from its first step

Process Overview

28nm Planar Flow: Process Overview

Introduction

Front-End-of-Line (FEOL)

Active Area and Isolation

Key integration ideas

Module Distribution

Step index