40nm BSI CMOS Image SensorPreview

Metal 0 step, which typically utilizes tungsten or highly stable conductive plugs for local middle-of-line (MOL) contacts, M1 initiates the low-resistance copper dual-damascene scheme [A1]. Furthermore, compared to the upper Metal 2 through Metal 4 routing layers, M1 exhibits the tightest pitch and smallest critical dimensions, placing the most stringent demands on feature filling capability (Engineering Practice). This step directly follows the deposition of a Ta-based liner and a physical vapor deposition (PVD) Cu seed layer, which together provide a conductive cathode surface while preventing subsequent Cu diffusion into the surrounding inter-layer dielectric [A1]. The primary objective of this process is to completely fill the submicrometer trenches and vias without voids, establishing a continuous and planarizable overburden layer required for the subsequent chemical mechanical polishing (CMP) step [P1]. The deposition is executed via an electrochemical copper deposition (ECD) process, where an externally applied electric field drives aqueous Cu2+ ions to the wafer surface for reduction into metallic copper atoms [P1]. To achieve void-free filling in high-aspect-ratio structures, a bottom-up superfilling mechanism is induced through a complex interplay of organic bath additives [P3]. Organic molecules, such as bis(3-sulfopropyl) disulfide (SPS) and polyethylene glycol (PEG), establish a spatially selective deposition inhibition effect [P3]. Due to restricted molecular diffusion within narrow submicrometer vias, a concentration gradient of these additives forms between the via opening and the bottom [P3]. This gradient causes stronger suppression at the upper surface and enhanced electrochemical reduction kinetics at the via bottom, allowing the vertical deposition rate to exceed the conformal sidewall growth rate [P3]. Copper is selected as the primary interconnect material over traditional aluminum because its lower electrical resistivity and superior resistance against electromigration significantly mitigate RC delay in integrated circuits [P3]. Wet electrochemical deposition is preferred over physical vapor deposition (PVD) or chemical vapor deposition (CVD) because it offers superior bottom-up filling capability, effectively preventing the formation of key-hole voids in high-aspect-ratio dual-damascene structures [P1]. Process parameters, including the applied current waveform and bath chemistry, are carefully tuned to maximize the proportion of the Cu(111) crystallographic orientation [P1]. A strong Cu(111) texture is highly favored because it minimizes electron scattering and substantially prolongs electromigration lifetime, which are critical for long-term interconnect reliability [P1]. Furthermore, in-situ optical monitoring can be utilized to track bath chemistry and ensure the reduction reaction efficiency remains stable over the process run [P1]. At the 40nm technology node, the physical scaling of critical dimensions imposes a fundamental constraint on copper interconnect performance [A2]. As the interconnect cross-sectional area decreases, the protective barrier layer consumes an increasingly larger fraction of the total conductor volume, which fundamentally escalates local line resistance [A2]. Because electrons face increased size-dependent surface scattering at these dimensions, optimizing the initial plating state to reduce internal defect density is essential [P2]. Following the ECD process, an annealing step is typically employed to drive atomic rearrangement, promote grain coarsening, and reduce the final sheet resistance of the film [P2]. This thermal activation lowers the system's overall free energy and minimizes grain boundary scattering, ensuring the M1 layer meets the strict RC delay targets necessary for high-speed signal readout in 40nm BSI CMOS image sensors (Engineering Practice).