40nm BSI CMOS Image SensorPreview

ulk dielectric (ILD 1-2 Oxide) to create vertical pathways for interconnecting Metal 1 and Metal 2 [A2]. Following the Via 1 Photo step, this reactive ion etch (RIE) strictly removes the ILD 1-2 layer while preserving the underlying ILD 1-1 SiCN layer, which acts as a protective etch-stop layer [A2]. Unlike front-end pad oxide etches that prepare the silicon surface or thin hard mask etches for pattern transfer, this step requires high aspect ratio etching through a thick bulk dielectric [P3]. The process immediately precedes the SiCN etch and photoresist ashing, setting up a via-first dual damascene sequence that will eventually be followed by the Metal 2 trench patterning [A1]. The etching relies on a synergistic physicochemical process combining directional ion bombardment and radical-driven chemical reactions in a plasma environment [P1]. Fluorocarbon-based chemistry (e.g. (Engineering Practice), CF4 or CHF3) is typically utilized to generate reactive fluorine radicals alongside passivating fluorocarbon polymer precursors [P2]. High-energy ions accelerated across the plasma sheath break the strong Si-O bonds, allowing fluorine radicals to form volatile SiF4 byproducts [P1]. Simultaneously, the fluorocarbon radicals deposit a protective polymer film on the via sidewalls, preventing lateral isotropic chemical etching and ensuring a highly anisotropic profile [P3]. This delicate balance between ion directionality and chemical selectivity determines the final sidewall angle and overall via geometry [P3]. Fluorocarbon plasmas are selected because their polymerization characteristics provide excellent etch selectivity of SiO2 over the underlying SiCN etch-stop layer and the photoresist mask [P2]. Increasing the carbon-to-fluorine ratio in the feed gas mixture enhances sidewall passivation but reduces the overall etch rate, necessitating precise parameter tuning [P3]. Higher radio-frequency (RF) bias power increases incident ion energy, which improves the vertical etch rate and anisotropy but simultaneously increases the risk of physical damage to the masking layers and underlying structures [P1]. Furthermore, aspect-ratio-dependent etching (RIE lag) causes smaller via openings to etch more slowly than larger ones due to restricted transport of neutrals and ions into deep cavities [P2]. The differential etch selectivity between the oxide and the SiCN layer is exploited to safely terminate the etch, preventing punch-through into the underlying metal structures before the subsequent SiCN open step [A2]. In 40nm BSI CMOS image sensor technology, the continuous scaling of interconnect dimensions fundamentally increases RC delay and cross-talk capacitance between tightly packed vias [T2]. To mitigate via-to-line misalignment caused by lithographic overlay limits, self-aligned strategies and highly selective etch-stop layers are critical to prevent electrical shorting [A1]. Strict control of the via profile is required, as any deviation in the sidewall angle or critical dimension (CD) directly impacts the subsequent metal barrier deposition and copper fill, directly altering the interconnect series resistance [A1].