40nm BSI CMOS Image SensorPreview

Sensors, thinning the silicon wafer exposes the backside epitaxial layer, creating a physical boundary heavily populated with dangling bonds and crystalline defects [T1]. These interface defects act as generation-recombination centers that severely increase dark current and degrade the signal-to-noise ratio of the sensor [P5]. The Back Passivation Ion Implantation (IIP) step addresses this by introducing acceptor dopants into the backside silicon surface to form a highly doped, shallow accumulation layer [P1]. Positioned immediately after the "Backside Passivation IIP - Photo" lithography step, this process uses the patterned photoresist to selectively mask and implant specific pixel arrays or peripheral regions [T1]. Following this step and subsequent ashing/cleaning, the wafer will undergo a specialized vacuum bake to activate the dopants and repair lattice damage, constrained by the strict thermal budget of the existing front-side metallization [P6]. The fundamental physical mechanism at work is field-effect passivation, which relies on a heavy dopant concentration to induce steep energy band bending near the silicon surface [P1]. By introducing acceptor impurities that shift the local Fermi level close to the valence band, the implant creates a strong built-in electric field [T1]. This localized electric field selectively repels minority carriers (electrons in the p-type epitaxial layer) away from the defective backside surface, drastically reducing their probability of interacting with interface trap states [P1]. Because the implanted layer is extremely shallow, the dopants are highly susceptible to interface segregation during subsequent thermal activation, where gradients in chemical potential and stress drive the dopant atoms to pile up exactly at the Si-SiO2 boundary [P5]. This interfacial pile-up is highly beneficial for BSI devices, as it maximizes the concentration of electrically active dopants—and thus the repulsive electric field—precisely where the defect density is the highest [P5]. Boron or boron-based molecular ions (such as BF2) are selected for this step because they act as efficient shallow acceptors in silicon, readily providing the holes required for the surface accumulation layer [T1]. The implantation energy must be kept extremely low to ensure an ultra-shallow junction profile, which minimizes the thickness of the highly doped "dead zone" where incident short-wavelength (blue) light is absorbed without contributing to the photocurrent [P5]. Furthermore, because this process occurs late in the integration flow, the wafer can only tolerate low-temperature thermal budgets to prevent degradation of the front-side Cu/low-k interconnects [P6]. This restricted thermal budget limits the degree of damage repair and activation, increasing the risk of transient enhanced diffusion (TED) if point defects are not managed effectively [P6]. Consequently, the implant dose and energy must be carefully co-optimized to provide sufficient active dopants for robust field-effect passivation while strictly avoiding excessive lattice amorphization that cannot be resolved by low-temperature baking [P6]. At the 40nm technology node, the extreme scaling of the pixel pitch demands high spatial precision during the masked implantation process [P7]. Lateral ion scattering, driven by nuclear stopping interactions as ions decelerate through the photoresist mask edges, can cause dopants to emerge at shallow angles and implant into unintended adjacent regions [P7]. This mask-edge proximity effect can alter the effective doping concentration of neighboring sub-pixels or isolation structures, requiring precise control of the implant tilt angle and the resist sidewall profile to maintain pixel-to-pixel uniformity [P7].