Rapid Thermal Processing - 40nm

Conversely, targeting too thin an oxide via reduced thermal input allows excessive interface traps to persist due to insufficient chemical bonding .

The Rapid Thermal Processing (RTP) step is executed immediately after the vacuum bake and preceding the RF plasma and high-k dielectric (AlO/TaO) de

position to prepare the backside silicon surface . The primary function of this step is to grow a precisely controlled, ultra-thin thermal silicon dioxide (SiO2) interlayer and to thermally heal crystalline defects induced by prior backside thinning and etch steps . By forming strong Si–O bonds at the silicon surface, this step directly reduces dangling bonds and lowers the interface trap density ($D_{it}$), which is critical for suppressing dark current in Backside-Illuminated (BSI) CMOS Image Sensors . This step establishes the foundation for the subsequent passivation layers, as the structural quality of this interfacial oxide dictates the device's ultimate balance between chemical and field-effect passivation . The physical mechanism relies on the rapid, thermally driven reaction between the crystalline silicon substrate and an oxidizing ambient to form a high-quality, ordered interface . In intrinsic silicon, surface defects and broken covalent bonds introduce parasitic energy states within the bandgap, acting as generation-recombination centers that increase leakage . The RTP process provides the intense, transient thermal activation energy required for oxygen to react with these dangling bonds, neutralizing electrically active defects through robust chemical passivation . Furthermore, growing a dense, thin SiO2 layer at high temperatures creates a stable structural template that can suppress subsequent interface degradation during downstream processing . The rapid heating and cooling cycles inherent to RTP minimize unwanted dopant diffusion in the underlying pixel structures, exploiting the principle that the thermal diffusion length is strictly a function of the time-temperature profile . RTP is selected over conventional batch furnace oxidation because it tightly restricts the overall thermal budget, preventing the degradation of lower-layer metal interconnects and precise dopant profiles . The key tradeoff in parameter selection is the target oxide thickness: increasing the RTP temperature or soak time thickens the SiO2 layer, which improves chemical passivation but simultaneously screens the fixed charges ($Q_f$) of the subsequently deposited high-k AlO layer, thereby weakening field-effect passivation . Conversely, targeting too thin an oxide via reduced thermal input allows excessive interface traps to persist due to insufficient chemical bonding . Therefore, process parameters such as peak temperature and ramp rates must be carefully co-optimized to yield an ultra-thin interfacial layer that perfectly balances interfacial bonding quality with the electrostatic requirements of the MIS structure . In 40nm BSI technology, the photo-collection volume is heavily reliant on the deeply thinned backside silicon, making the surface-to-volume ratio extremely high (Engineering Practice). At this scaled node, dark current variations become highly non-uniform across the dense pixel array if the surface is not perfectly passivated . The RTP step provides a highly uniform chemical interface that acts as a physical buffer, mitigating the severe plasma-induced damage expected from the subsequent low-temperature plasma-enhanced atomic layer deposition (PEALD) processes .

[High] Weakened Field-Effect Passivation: If the RTP time or temperature exceeds the optimal window, an overly thick SiO2 layer will form . A thick SiO2 interlayer physically screens the internal electric field generated by the fixed charges ($Q_f$) in the subsequent high-k AlO film, diminishing the electrostatic repulsion of minority carriers away from the interface and reducing field-effect passivation efficacy .
[High] High Dark Current due to Insufficient Chemical Passivation: If the RTP thermal budget is too low, the oxidation reaction will be incomplete, leaving numerous unpassivated dangling bonds at the Si/SiO2 interface . These interface traps ($D_{it}$) act as carrier generation centers within the silicon bandgap, severely increasing dark current and white pixel defects in the BSI sensor .
[Medium] Thermal Degradation of Underlying Structures: Because backside processing occurs after front-side device fabrication, excessive peak temperatures during RTP can cause undesirable dopant diffusion or degradation in the underlying CMOS structures . This violates the strict thermal budget constraints required to maintain abrupt ultra-shallow junctions in advanced nodes .
[Medium] Vulnerability to Subsequent Plasma Damage: If the thermally grown oxide layer is structurally compromised or too thin due to RTP non-uniformity, the subsequent RF plasma and PEALD high-k deposition steps can penetrate the oxide and introduce new interfacial defects or oxygen vacancies . This plasma-induced damage directly deteriorates the interface quality, necessitating further post-deposition curing to recover device performance .

Conversely, targeting too thin an oxide via reduced thermal input allows excessive interface traps to persist due to insufficient chemical bonding .

The Rapid Thermal Processing (RTP) step is executed immediately after the vacuum bake and preceding the RF plasma and high-k dielectric (AlO/TaO) de

[High] Weakened Field-Effect Passivation: If the RTP time or temperature exceeds the optimal window, an overly thick SiO2 layer will form . A thick SiO2 interlayer physically screens the internal electric field generated by the fixed charges ($Q_f$) in the subsequent high-k AlO film, diminishing the electrostatic repulsion of minority carriers away from the interface and reducing field-effect passivation efficacy .
[High] High Dark Current due to Insufficient Chemical Passivation: If the RTP thermal budget is too low, the oxidation reaction will be incomplete, leaving numerous unpassivated dangling bonds at the Si/SiO2 interface . These interface traps ($D_{it}$) act as carrier generation centers within the silicon bandgap, severely increasing dark current and white pixel defects in the BSI sensor .
[Medium] Thermal Degradation of Underlying Structures: Because backside processing occurs after front-side device fabrication, excessive peak temperatures during RTP can cause undesirable dopant diffusion or degradation in the underlying CMOS structures . This violates the strict thermal budget constraints required to maintain abrupt ultra-shallow junctions in advanced nodes .
[Medium] Vulnerability to Subsequent Plasma Damage: If the thermally grown oxide layer is structurally compromised or too thin due to RTP non-uniformity, the subsequent RF plasma and PEALD high-k deposition steps can penetrate the oxide and introduce new interfacial defects or oxygen vacancies . This plasma-induced damage directly deteriorates the interface quality, necessitating further post-deposition curing to recover device performance .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges