Consequently, the plasma chemistry must be tuned to an optimized carbon-to-fluorine ratio; excessive fluorine leads to sidewall bowing and low-k damage, while excess carbon causes etch-stop phenomena due to over-polymerization .
The ILD 1-2 Oxide Etch step is a critical back-end-of-line (BEOL) p
rocess designed to form the Metal 2 interconnect trenches within the interlayer dielectric . Following the Metal 2 photolithography and the preceding ILD 1-1 SiCN via/etch stop layer opening, this step subtractively defines the horizontal routing pathways for the subsequent Ta-based liner and copper seed deposition . Unlike front-end oxide etches (such as pad oxide or spacer etches) that interface directly with robust crystalline silicon, this BEOL step typically processes carbon-doped or structurally modified low-k oxides (SiOCH) where preserving the delicate bulk dielectric constant is paramount . Furthermore, the trench etch must precisely terminate at a controlled depth or upon a middle etch-stop layer to ensure reliable dual-damascene integration and avoid via-to-trench misalignment . The fundamental mechanism of this step relies on reactive ion etching (RIE) utilizing fluorocarbon-based plasmas . Within the low-pressure plasma discharge, electron collisions generate active neutral fluorine radicals and charged fluorocarbon ions (CFx+) . The fluorine radicals chemically attack the silicon-oxygen bonds to form highly volatile byproducts such as SiF4 and COx, which are subsequently pumped out of the chamber . Concurrently, directional ion bombardment driven by the applied RF bias accelerates vertically into the trench, breaking molecular bonds at the bottom and supplying the activation energy needed for the chemical reaction to proceed . Meanwhile, the carbon-containing radicals dynamically deposit a passivating fluoropolymer layer on the trench sidewalls, effectively suppressing lateral chemical etching and yielding a highly anisotropic, vertical profile . Parameter selection for this etch is dictated by the delicate balance between etching, polymerization, and material selectivity . As integrated circuit dimensions shrink toward the 40nm node, device performance becomes increasingly constrained by interconnect RC delay, necessitating the use of low-k oxide films . These slightly porous or carbon-doped SiOCH networks are mechanically fragile and highly susceptible to plasma-induced carbon depletion . Consequently, the plasma chemistry must be tuned to an optimized carbon-to-fluorine ratio; excessive fluorine leads to sidewall bowing and low-k damage, while excess carbon causes etch-stop phenomena due to over-polymerization . Additionally, the process must maintain high etch selectivity against the underlying SiCN layer to prevent over-etching into the previously formed vias, a dynamic governed by the differing bond energies and surface passivation rates of the respective materials . Substrate temperature is also actively controlled to modulate the volatility of etch byproducts and minimize micro-masking . At the 40nm technology node, stringent overlay budgets and tight metal pitches amplify the complexity of the trench etch . To achieve seamless geometric alignment between the Metal 2 trench and the underlying via structure, advanced co-etch strategies involving sacrificial via-fill materials are frequently employed . The etch plasma synchronously clears the oxide to form the trench while removing the sacrificial organic material inside the via at a precisely matched rate . If the respective etch rates are not perfectly synchronized, the resulting structural anomalies—such as via chamfering or sidewall faceting—can dramatically increase local parasitic capacitance and compromise device reliability .
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