40nm BSI CMOS Image SensorPreview

ceded by the MET2 chemical-mechanical polishing (CMP) and the deposition of ILD 2-1, which often acts as a thin cap or etch stop layer to prevent copper diffusion into the bulk dielectric [P4]. ILD 2-2 provides the structural matrix for the upcoming Via 2 dual-damascene patterning steps (Engineering Practice). Unlike upper-level dielectrics such as ILD 6-2, which frequently employ thicker, standard k-value oxides for robust power routing and structural integrity [A1], ILD 2-2 operates at a tightly pitched lower metal level where strict low-k materials are mandatory to minimize inter-layer and intra-layer capacitive coupling [P2]. Reducing this capacitance is critical to alleviating the dynamic power consumption and interconnect RC delay issues that dominate modern scaled devices [T2]. This deposition utilizes Plasma-Enhanced Chemical Vapor Deposition (PECVD) to form a carbon-doped silicon oxide (SiCOH) network [P1]. Within the RF plasma environment, high-energy electrons collide with organosilicon precursors, fragmenting Si-C and C=C bonds to generate highly reactive radicals [P3]. These radicals subsequently adsorb and cross-link on the wafer surface, while the introduction of an oxidant (such as O2) dictates the formation of the rigid inorganic Si-O-Si backbone [P3]. The deliberate inclusion of bulky organic groups, such as methyl or vinyl ligands, inherently lowers the film's atomic density and electronic polarizability, thereby achieving the desired low dielectric constant [P3]. Furthermore, varying the deposition plasma power directly modulates the ion bombardment energy; higher plasma power promotes denser cross-linking, which subsequently increases both the mechanical modulus and the bulk dielectric constant [P1]. The selection of PECVD SiCOH is driven by the fundamental trade-off between electrical performance and thermo-mechanical stability [P1]. PECVD allows film deposition at appropriately low thermal budgets, which is essential to prevent the underlying Cu/Ta metallization from undergoing premature agglomeration or barrier failure [P4]. To further depress the k-value, a sacrificial organic phase (porogen) can be co-deposited and later outgassed via thermal annealing to create a nanoporous structure [P1]. However, this induced porosity inherently weakens the structural continuity of the network, making the film highly susceptible to damage during subsequent processing [P1]. At the 40nm node, the tight interconnect pitch demands a highly optimized k-value while maintaining sufficient hardness to survive the aggressive Via 2 etching and cleaning processes [P2]. If not carefully optimized, reductive or oxidizing plasmas used in subsequent photoresist stripping can cause severe surface carbon depletion and pore collapse, resulting in a localized densified layer that introduces severe k-value drift [P2].