During optical exposure, light passes through the photomask to chemically alter the resist, but systematic distortions from optical interference must be countered using advanced optical proximity correction (OPC) techniques.
In depth
The METAL 2 TRENCH - Photo step is a critical back-end-of-line (BEOL) l
ithography process that defines the lateral routing structures for the second metal layer . Prior to this step, the V1 vias were etched into the inter-layer dielectric (ILD), establishing a via-first dual-damascene integration scheme. Unlike Frontside Deep Trench or STI photo steps that pattern bulk silicon for isolation, or Metal 0/1 steps that interface directly with the sensitive device contact levels, the Metal 2 step focuses strictly on optimizing routing density and minimizing interconnect RC delay. The primary objective of this step is to pattern the trench openings in the photoresist directly above the pre-existing vias, preparing the wafer for the subsequent ILD trench etch.
The physical mechanism of this step relies on optical lithography, where the theoretical resolution limit is governed by the Rayleigh criterion connecting exposure wavelength and numerical aperture. Because the underlying etched vias present significant surface topography, a sacrificial gap-fill material or bottom anti-reflective coating (BARC) must first be spin-coated to fill the vias and planarize the surface. This gap-filling treatment is mathematically and physically essential to produce a highly planar surface, ensuring that the subsequently coated photoresist layer maintains a uniform thickness across the wafer. During optical exposure, light passes through the photomask to chemically alter the resist, but systematic distortions from optical interference must be countered using advanced optical proximity correction (OPC) techniques. Following exposure, the development process removes the soluble portions of the resist, leaving a physical trench mask that is precisely aligned over the filled vias.
The via-first integration method is explicitly selected because it minimizes the complex defect propagation associated with etching deep vias through pre-existing trenches. However, the physical overlay accuracy between the newly patterned trench and the underlying via is paramount; misalignment can result in via chamfering, which introduces higher parasitic capacitance and short-circuit risks. Furthermore, the critical dimension (CD) of the patterned trench dictates the final copper volume, which must be carefully co-optimized with the surrounding low-k dielectric to balance electrical resistance against line-to-line capacitance. If the patterned trench is too narrow, the resulting reduced cross-sectional area will accelerate the directed diffusion of metal atoms, leading to early electromigration (EM) failure due to higher localized current densities.
For 40nm CMOS Image Sensor technology, the interconnect pitch requires tight overlay control, though it avoids the extreme double-patterning complexity seen in sub-nanoscale nodes. The photoresist chemistry and gap-fill materials must be precisely engineered to withstand capillary forces and prevent pattern collapse, which is a major systematic yield-limiting mechanism. Ultimately, the stringent control of surface planarity and CD in this lithography step prevents defect amplification during the subsequent low-k dielectric etch and copper metallization modules.
Risks & Challenges
[High] Trench-to-Via Misalignment: Lithography overlay errors cause the trench pattern to shift relative to the underlying V1 via . This geometric misalignment forces the subsequent trench etch to land off-center, causing via chamfering, elevated contact resistance, or potential via-trench leakage.
[High] Photoresist Pattern Collapse: Capillary forces acting on the photoresist sidewalls during the post-development rinse and dry phases can mechanically overcome the structural strength of the resist lines. This stress-induced mechanism is particularly dominant in dense BEOL patterns, resulting in systematic missing patterns and eventual open circuits.
[Medium] Incomplete Via Gap-Fill: If the sacrificial planarization material fails to completely fill the high-aspect-ratio underlying vias, local depressions form on the wafer surface. This topographic variation disrupts the planarity of the overlying photoresist, causing local depth-of-focus errors during exposure that manifest as line shorts or opens.
[Low] Line Edge Roughness (LER): Statistical variations in the lithography process and the granular nature of the photoresist polymer chain lead to microscopic waviness along the developed trench edges. This roughness transfers into the final copper trench, creating localized areas of elevated current density that act as early nucleation sites for electromigration voiding.