40nm BSI CMOS Image SensorPreview

resistive Ta-based liner and the subsequent bulk electrochemical plating (ECP) process [P4]. In the dual-damascene interconnect flow for 40nm BSI CMOS image sensors, this layer provides the necessary continuous cathode for uniform electrochemical Cu deposition [P4]. Since the preceding Ta-based liner has poor electrical conductivity and lacks the surface properties required for direct Cu electroplating, a high-purity metallic Cu layer must be deposited first [P3]. Unlike lower-level interconnects (such as MET1) which may have extremely tight pitches, or top-level routing metals which are much thicker, MET2 balances intermediate aspect ratios with stringent low-resistance requirements for high-speed image sensor signal routing (Engineering Practice). The physical mechanism of Cu seed deposition relies primarily on ionized physical vapor deposition (PVD) to achieve conformal coating within high-aspect-ratio trenches and vias [P4]. During this process, an applied wafer bias establishes a balance between incoming neutral Cu deposition and ionized Cu bombardment [P1]. This energetic bombardment induces localized resputtering, wherein Cu atoms deposited on the trench bottom are physically dislodged and redeposited onto the vertical sidewalls, thereby enhancing step coverage [P3]. The morphological evolution of the thin Cu film is governed by surface energy and interfacial wettability; because Cu exhibits relatively poor wetting on Ta-based substrates, the seed layer tends to agglomerate into isolated islands if the film is too thin [P3]. If the seed layer is structurally discontinuous, the subsequent electrodeposition will suffer from localized current density concentration, resulting in granular and rough deposit morphology that eventually causes filling voids [P4]. PVD remains the method of choice for 40nm technology because it avoids the higher resistivity and complex chemical reduction steps associated with emerging atomic layer deposition (ALD) Cu oxide methods [P2]. To optimize the process, parameters such as AC wafer bias and deposition time must be carefully co-optimized; a moderate bias ensures adequate bottom and sidewall coverage while actively suppressing excessive accumulation in the field regions [P1]. Furthermore, managing the seed-to-plate queue time is a critical operational parameter (Engineering Practice). Extending the queue time allows the highly reactive nano-scale Cu surface to oxidize or accumulate adventitious contamination [P4]. This oxidation reduces the effective nucleation density for the subsequent ECP step, prompting the formation of coarser, more separated electrodeposited Cu particles rather than a dense, continuous film [P4]. At the 40nm node, interconnect dimensions are small enough that traditional thick PVD seeds face severe step-coverage constraints, yet they generally do not necessitate entirely novel liner systems like chemical vapor deposited (CVD) Co, which are typically reserved for sub-nanoscale dimensions [P3]. Instead, optimizing the traditional PVD seed process through precise bias control and occasional thermally activated surface diffusion (reflow) allows the geometric aspect ratio to be effectively managed [P1]. By facilitating a "pre-filling" effect via surface energy gradients, the Cu seed can maintain a sufficiently large top opening prior to ECP, averting premature pinch-off and ensuring void-free gap-fill [P1].