Pre Litho Cleaning - 40nm

Semiconductor lithography relies on forming three-dimensional relief images in a light-sensitive polymer to define patterns for subsequent etching .

In the 40nm BSI CMOS Image Sensor process flow, the Pre Litho Cleaning step within the ILD2 module acts as a critical bridge between the ILD 2-2 Dep

osition and the Via 2 photolithography stages (Engineering Practice). Semiconductor lithography relies on forming three-dimensional relief images in a light-sensitive polymer to define patterns for subsequent etching . To achieve optimal pattern fidelity, the freshly deposited inter-level dielectric (ILD) must be completely free of airborne molecular contaminants, particle fallout, and chemical residues left over from the preceding plasma-enhanced or flowable deposition steps . As device geometries scale down to deep submicron and nanometer nodes, backend-of-line (BEOL) systematic defects—such as those originating from poor lithography pattern fidelity or photoresist thickness non-uniformity—increasingly dominate wafer yield loss . Therefore, this step ensures a pristine, chemically uniform surface that promotes proper adhesion of the bottom anti-reflective coating (BARC) and photoresist, which is essential for defining the highly dense Via 2 structures (Engineering Practice). The physical and chemical mechanism of this wet clean involves a delicate balance of dilute chemical dissolution and mechanical energy (e.g. (Engineering Practice), megasonic agitation) to overcome the van der Waals forces binding adventitious particles to the dielectric surface (Engineering Practice). During deposition processes like PECVD, energetic ion bombardment can leave unstable surface states or minor roughness on the dielectric . If left untreated, these local geometric variations interact with capillary forces during resist processing, drastically increasing the susceptibility of high-aspect-ratio patterns to mechanical instability and collapse . The cleaning chemistry selectively modifies the zeta potential of both the particulate contaminants and the ILD surface, inducing strong electrostatic repulsion that suspends the particles in the fluid boundary layer so they can be rinsed away (Engineering Practice). By controlling the surface topography and chemistry prior to lithography, this process stabilizes critical dimension (CD) control and suppresses defect amplification . The selection of cleaning agents for this step is heavily restricted by the material properties of the ILD 2-2 layer, which frequently incorporates low-k dielectric materials in advanced 40nm nodes (Engineering Practice). Conventional cleaning chemistries that are too aggressive may damage the underlying dielectric material or absorb into the pores of the ILD, thereby permanently increasing its dielectric constant . To prevent this, highly dilute aqueous mixtures are utilized, ensuring that the chemical etch rate of the dielectric remains essentially zero while still providing sufficient oxidative or solvating power to remove trace organics . The primary control parameters—temperature, chemical concentration, and physical agitation power—must be co-optimized; higher temperatures improve reaction kinetics for organic removal but narrow the safe process window regarding dielectric integrity (Engineering Practice). What distinguishes this specific Pre Litho Cleaning step from other similar cleans in the flow is its placement immediately preceding the critical Via 2 patterning in a dense BEOL stack (Engineering Practice). Unlike post-etch cleans that must strip tough tungsten or copper-containing polymeric residues , this step is purely focused on surface conditioning. In multi-level integrated circuit manufacturing, achieving near-perfect global and local planarity is critical because irregularities add up as layers are placed on top of each other, eventually pulling the surface out of the stringent depth of focus (DOF) of the photolithography system . By guaranteeing a defect-free and uniform surface at this precise juncture, the process mitigates the risk of interconnect line shorts and open circuits that would otherwise form during the subsequent dual-damascene etch and fill sequences .

[High] Photoresist Adhesion Failure: If the cleaning chemistry fails to adequately remove organic trace contaminants or properly condition the dielectric's surface energy, the subsequent photoresist layer will suffer from poor wetting and weak interface bonding . This weak adhesion directly leads to pattern collapse or missing patterns during the lithography development phase, a primary systematic defect mechanism in high-density submicron patterning .
[High] Low-k Dielectric Degradation: Using an improperly calibrated, overly aggressive cleaning solution can cause the chemicals to penetrate and absorb into the porous structure of the low-k ILD layer . This fundamentally alters the physical properties of the film, increasing its dielectric constant and introducing excessive parasitic capacitance that can degrade signal routing performance and cause signal delay .
[Medium] Particle-Induced Lithography Defocus: Incomplete removal of nanometer-scale particles originating from the deposition chamber can create localized topographical spikes (Engineering Practice). These micro-irregularities can shift the local wafer surface outside the strict depth of focus (DOF) limits of the photolithography scanner, causing distorted critical dimensions (CDs) that eventually manifest as electrical opens or shorts .
[Low] Surface Micro-Roughening: Extended chemical exposure times or excessively high process temperatures may inadvertently micro-etch the amorphous dielectric surface . While controlled wet etching can theoretically smooth specific crystal planes like silicon (111) , isotropic attack on amorphous oxides generates non-uniform pitting, which translates into severe line-edge roughness during the subsequent pattern transfer and reactive ion etching (RIE) steps .

Semiconductor lithography relies on forming three-dimensional relief images in a light-sensitive polymer to define patterns for subsequent etching .

In the 40nm BSI CMOS Image Sensor process flow, the Pre Litho Cleaning step within the ILD2 module acts as a critical bridge between the ILD 2-2 Dep

[High] Photoresist Adhesion Failure: If the cleaning chemistry fails to adequately remove organic trace contaminants or properly condition the dielectric's surface energy, the subsequent photoresist layer will suffer from poor wetting and weak interface bonding . This weak adhesion directly leads to pattern collapse or missing patterns during the lithography development phase, a primary systematic defect mechanism in high-density submicron patterning .
[High] Low-k Dielectric Degradation: Using an improperly calibrated, overly aggressive cleaning solution can cause the chemicals to penetrate and absorb into the porous structure of the low-k ILD layer . This fundamentally alters the physical properties of the film, increasing its dielectric constant and introducing excessive parasitic capacitance that can degrade signal routing performance and cause signal delay .
[Medium] Particle-Induced Lithography Defocus: Incomplete removal of nanometer-scale particles originating from the deposition chamber can create localized topographical spikes (Engineering Practice). These micro-irregularities can shift the local wafer surface outside the strict depth of focus (DOF) limits of the photolithography scanner, causing distorted critical dimensions (CDs) that eventually manifest as electrical opens or shorts .
[Low] Surface Micro-Roughening: Extended chemical exposure times or excessively high process temperatures may inadvertently micro-etch the amorphous dielectric surface . While controlled wet etching can theoretically smooth specific crystal planes like silicon (111) , isotropic attack on amorphous oxides generates non-uniform pitting, which translates into severe line-edge roughness during the subsequent pattern transfer and reactive ion etching (RIE) steps .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges