40nm BSI CMOS Image SensorPreview

T2) module, the bulk copper overburden is first planarized during the main Cu CMP step [P3]. Following this, the Ta-based liner CMP step is executed to completely remove the exposed Ta/TaN barrier layer from the field dielectric regions [P3]. This step is critical because leaving any conductive liner residue on the field oxide would result in electrical shorting between adjacent MET2 lines (Engineering Practice). Furthermore, this barrier CMP step planarizes the entire interconnect stack, including the copper in trenches, sidewall liner, and surrounding dielectric, to meet the targeted final Metal 2 line height [P3]. By achieving a globally planarized surface, this step prepares the wafer for subsequent Post CMP Cleaning and the deposition of the ILD 2-1 layer [P3]. While similar Ta-liner CMP steps occur at other metal levels, this specific step handles the pattern densities and layout dimensions specific to the MET2 interconnects of the 40nm BSI CIS architecture [P3]. The physical and chemical mechanisms of Ta-based liner removal differ significantly from bulk copper polishing [P3]. Tantalum and tantalum nitride are chemically highly resistant materials that provide a primary diffusion barrier function [P2]. In standard acidic copper-clearing slurries, the removal of the Ta adhesion and diffusion barrier is purely mechanical, which can lead to severe structural overpolishing and dielectric erosion [P1]. To avoid this, barrier CMP utilizes specially formulated slurries that introduce specific chemical oxidants to modify the surface state of the Ta layer [P3]. The chemical component oxidizes the Ta/TaN surface, while the mechanical component, driven by abrasive particles under an applied polishing pad pressure, shears off the oxidized reaction layer [P1]. This synergistic action of chemical oxidation and mechanical removal follows Preston's law, where the material removal rate is proportional to the applied pressure and relative velocity [P3]. The primary objective in slurry selection and parameter tuning for barrier CMP is achieving the correct removal rate selectivity between the Ta liner, the copper features, and the underlying dielectric [P3]. An ideal process must yield no liner residuals while minimizing topography defects such as copper dishing and dielectric erosion [P3]. If the slurry chemistry etches copper too aggressively during the barrier removal phase, the soft copper lines will dish below the dielectric level, degrading interconnect resistance and causing subsequent photolithography depth-of-focus issues [P3]. Therefore, the barrier CMP slurry is typically designed to have a high removal rate for Ta/TaN but a heavily suppressed removal rate for Cu, often by using corrosion inhibitors that passivate the copper surface [P3]. The parameter interaction directions dictate that increasing the oxidant concentration or adjusting the mechanical downforce must be carefully balanced; excessive force increases mechanical wear on the soft dielectric, while insufficient chemical action leaves unyielding Ta residues [P1]. At the 40nm technology node, the scaling of interconnect line widths and spacings introduces distinct challenges for the Ta-based liner CMP process [P3]. As feature sizes shrink, the local contact area, stress distribution, and slurry transport dynamics on the wafer surface change significantly [P3]. Removal rates and selectivities measured on unpatterned blanket wafers cannot be directly extrapolated to these high-density patterned structures [P3]. The process becomes highly sensitive to local pattern density, meaning that regions with dense MET2 lines may experience different effective polishing pressures compared to isolated features [P3]. Consequently, strict process monitoring and advanced endpoint detection are required to ensure the thin 40nm node barrier is fully cleared without causing severe dielectric erosion or compromising the barrier's integrity against copper diffusion [P2].