40nm BSI CMOS Image SensorPreview

rm the second-level conductive interconnects within the 40nm CMOS Image Sensor architecture [A1]. Following the physical vapor deposition of a Ta-based diffusion barrier and a conformal Cu seed layer, this step utilizes electroplating to completely fill the high-aspect-ratio vias and trenches defined in the dielectric [A1]. Copper is universally employed for these intermediate routing layers because of its low electrical resistance and superior electromigration performance compared to legacy aluminum interconnects [A1]. Unlike the Metal 0 W deposition, which serves as a highly refractory local contact to the device source/drain regions, M2 routing provides intermediate-level signal transmission and structural foundations for subsequent thicker global routing layers like Metal 3 and Metal 4 [A1]. Furthermore, this step directly prepares the wafer for the subsequent Chemical Mechanical Planarization (CMP) module, which relies on a continuous and uniformly deposited bulk Cu overburden to planarize the interconnect structure [A1]. The core physical mechanism driving this step is electrochemical deposition governed by Faraday’s laws of electrolysis and charge-transfer kinetics at the cathode surface [P1]. Because Cu electrodeposition begins the moment the live wafer enters the plating bath, the liquid-solid interface immediately enters a nonequilibrium state characterized by transient diffusion and adsorption processes [P2]. To achieve void-free, bottom-up fill in nanometer-scale dual-damascene structures, the plating bath employs a multi-component organic additive system comprising an inhibitor, typically polyethylene glycol (PEG), and an accelerator, typically bis(3-sulfopropyl) disulfide (SPS), alongside chloride ions [P2]. On short time scales, the transport and adsorption of these additives are restricted by the via geometry, creating a spatial concentration gradient [P2]. This geometry-constrained transient diffusion results in lower inhibitor coverage and a relative enrichment of the accelerator at the bottom of the via, which locally accelerates the reduction of Cu²⁺ ions and triggers bottom-up growth [P2]. As the trench fills and the local effective area shrinks, longer-time-scale interactions between the accelerator and inhibitor amplify the deposition rate differential between the top and bottom, stabilizing the preferential bottom-up growth until the feature is fully sealed [P2]. Electroplating is selected over physical or chemical vapor deposition for bulk Cu fill because it uniquely enables this chemically modulated bottom-up growth, which is essential for preventing pinch-off and void formation in high-aspect-ratio features [P2]. Copper must be strictly isolated from the surrounding silicon and inter-metal dielectrics by the preceding Ta-based liner, as bare Cu rapidly diffuses through oxides and acts as a contamination source that can destroy device functionality [A1]. The kinetics of the deposition process are highly sensitive to the applied current waveform, additive concentrations, and bath temperature, which interact to modulate mass transport and interfacial concentration gradients [P1]. For example, increasing the plating current density accelerates the global reduction rate but risks depleting the local Cu²⁺ concentration inside the vias before bottom-up fill can complete [P2]. Simultaneously, careful control of the electrolyte hydrodynamics via wafer rotation and fluid flow ensures a stable boundary layer, preventing non-uniform current distribution across the wafer surface [P1]. At the 40nm technology node, the dimensions of the M2 trenches and vias introduce severe scaling challenges, particularly regarding the increasing influence of electron scattering at interfaces and grain boundaries [P3]. As interconnect pitches decrease, the proportion of the cross-sectional area consumed by the resistive Ta-based barrier layer increases, effectively reducing the available volume for the highly conductive Cu bulk [P3]. Consequently, the transient diffusion models that govern the bottom-up fill must be tightly optimized, as steady-state diffusion assumptions are no longer sufficient to explain the dynamic morphological evolution of sub-nanoscale structures [P2]. The resulting electroplated film must also be optimized for subsequent thermal steps that drive atomic rearrangement and reduce impurity content, thereby lowering the final resistivity of the Cu interconnect to mitigate the RC delay inherent to advanced logic and sensor designs [P3].