ILD 2-1 SiCN Etch - 40nm

During the SiCN etch, a highly selective fluorinated chemistry, such as CF4/O2 or CHF3, is typically selected to maintain structural fidelity .

In the V2 module, the process flow requires establishing electrical contact between Metal 2 and the upcoming Metal 3 layer (Engineering Practice). The

previous ILD 2-2 Oxide Etch step creates the via cavity through the main interlayer dielectric but intentionally stops on the underlying ILD 2-1 layer, which is typically a silicon carbonitride (SiCN) etch-stop and copper diffusion barrier . The primary objective of the ILD 2-1 SiCN Etch is to punch through this remaining hermetic barrier to expose the underlying Metal 2 surface . By physically exposing the metal surface, this step minimizes via contact resistance, a critical parameter for overall interconnect RC delay performance . This step is distinct from similar SiCN etches (like ILD 1-1 or 3-1) because it specifically bridges the M2 to M3 interconnect levels, requiring precise tuning to accommodate the specific via aspect ratios and underlying M2 metal densities of the 40nm node . The physical mechanism of this etch step relies on reactive ion etching (RIE) driven by fluorinated plasma chemistry . Specifically, fluorine atoms and carbon-fluorine radicals (CFx) generated in the plasma chemically react with the Si-C and Si-N bonds of the SiCN layer to form volatile byproducts such as SiF4 and carbon oxides, which are subsequently pumped away from the chamber . Simultaneously, physical ion bombardment accelerates the desorption of these reaction products and breaks surface bonds, providing the necessary anisotropy to maintain straight via sidewalls . The etch selectivity between the SiCN layer and the overlying ILD oxide is a critical mechanism; fluorinated gas mixtures must be carefully tuned to ensure the SiCN is removed without excessively eroding the surrounding low-k dielectric . Furthermore, the underlying metal acts as a physical stop, but the plasma must not sputter excessive metal back onto the via sidewalls, which could cause severe reliability issues . SiCN is specifically selected as the etch-stop and barrier layer because of its ability to provide a hermetic seal against copper and moisture diffusion when its mass density exceeds 2.0 g/cm³ . During the SiCN etch, a highly selective fluorinated chemistry, such as CF4/O2 or CHF3, is typically selected to maintain structural fidelity . CHF3 chemistries are strongly polymerizing, which helps coat the sidewalls with a fluorocarbon polymer to protect the via critical dimension (CD) during the SiCN punch-through . However, the use of highly polymerizing gases must be balanced against the risk of leaving thick fluorocarbon residues on the exposed metal (Engineering Practice). These residues require subsequent removal by stripping or reductive N2/H2 plasmas, which can induce their own competing processes of material removal and surface densification on the surrounding low-k ILD . The interaction between ion kinetic energy and radical chemical activity determines the final surface morphology and penetration depth of the etch . At the 40nm node, the continued scaling of device dimensions dramatically increases the impact of interconnect parasitic capacitance, necessitating the use of low-k or porous ILD materials alongside the SiCN barrier . As the via critical dimension shrinks, the aspect ratio increases, making it more challenging for reactive species to reach the via bottom to clear the SiCN layer . The plasma parameters must be tightly controlled to prevent plasma-induced damage or densification of the exposed low-k oxide sidewalls, which can inadvertently increase the effective dielectric constant and degrade RC performance . Additionally, preserving the geometric integrity of the via during this SiCN punch-through is essential to prevent self-alignment failures or subsequent time-dependent dielectric breakdown (TDDB) degradation caused by electric field concentration .

[High] High Contact Resistance (Via Open): Incomplete removal of the SiCN etch stop layer leaves a highly resistive dielectric barrier between the via plug and the underlying Metal 2 . This failure occurs if the fluorinated plasma etch rate drops or if polymerizing CFx radicals excessively passivate the via bottom during the reaction .
[High] Low-k ILD Plasma Damage (k-value drift): During the SiCN punch-through, radical diffusion and ion bombardment can alter the exposed sidewalls of the overlying porous low-k ILD . Reactive species deplete carbon from the Si-O-C network, causing surface densification and pore collapse, which increases the dielectric constant and degrades interconnect capacitance .
[Medium] Metal Sputtering and Sidewall Contamination: Over-etching into the underlying copper layer causes metal atoms to be physically sputtered by high-energy ions from the plasma . These metal atoms redeposit on the dielectric via sidewalls, creating leakage paths that degrade the time-dependent dielectric breakdown (TDDB) reliability of the localized interconnect structure .
[Low] Via Misalignment and Dielectric Shorting: If the SiCN etch process exhibits poor anisotropy, lateral etching can excessively erode the etch-stop layer sideways . This uncontrolled lateral expansion can inadvertently expose adjacent conductive structures or cause the via to short to nearby lines, particularly when electric fields concentrate at these compromised crossover regions .

During the SiCN etch, a highly selective fluorinated chemistry, such as CF4/O2 or CHF3, is typically selected to maintain structural fidelity .

In the V2 module, the process flow requires establishing electrical contact between Metal 2 and the upcoming Metal 3 layer (Engineering Practice). The

[High] High Contact Resistance (Via Open): Incomplete removal of the SiCN etch stop layer leaves a highly resistive dielectric barrier between the via plug and the underlying Metal 2 . This failure occurs if the fluorinated plasma etch rate drops or if polymerizing CFx radicals excessively passivate the via bottom during the reaction .
[High] Low-k ILD Plasma Damage (k-value drift): During the SiCN punch-through, radical diffusion and ion bombardment can alter the exposed sidewalls of the overlying porous low-k ILD . Reactive species deplete carbon from the Si-O-C network, causing surface densification and pore collapse, which increases the dielectric constant and degrades interconnect capacitance .
[Medium] Metal Sputtering and Sidewall Contamination: Over-etching into the underlying copper layer causes metal atoms to be physically sputtered by high-energy ions from the plasma . These metal atoms redeposit on the dielectric via sidewalls, creating leakage paths that degrade the time-dependent dielectric breakdown (TDDB) reliability of the localized interconnect structure .
[Low] Via Misalignment and Dielectric Shorting: If the SiCN etch process exhibits poor anisotropy, lateral etching can excessively erode the etch-stop layer sideways . This uncontrolled lateral expansion can inadvertently expose adjacent conductive structures or cause the via to short to nearby lines, particularly when electric fields concentrate at these compromised crossover regions .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges