40nm BSI CMOS Image SensorPreview

40nm BSI CMOS Image Sensor packaging flow [A1]. It follows the sequential removal of overlying ILD 6 and ILD 5 layers and immediately precedes the ILD 4-1 SiCN etch [P1]. The primary objective is to selectively remove the bulk silicon dioxide of the fourth interlayer dielectric tier to progress toward the underlying metal bond pad [P1]. What distinguishes this step from front-end oxide etches (such as shallow trench isolation or gate spacer etches) is its role in creating a deep, large-area vertical shaft through a complex multi-tier dielectric stack rather than defining fine transistor-level features [P3]. By alternating between thick oxide etches and thin SiCN barrier etches, the process tightly controls the etch depth and profile, preventing catastrophic punch-through into the sensitive metal structures below [P3]. The etching of SiO2 is fundamentally driven by plasma-assisted reactive ion etching (RIE), which relies on the synergistic interaction between neutral fluorocarbon radicals and directional ion bombardment [P4]. In the plasma, fluorocarbon feed gases dissociate to provide fluorine radicals that react with surface silicon atoms to form volatile silicon fluorides (SiFx) [P4]. Simultaneously, carbon-based species deposit a mixing layer of fluorocarbon polymer on the exposed surfaces [P4]. On the SiO2 surface, oxygen released from the lattice continuously combusts this polymer, keeping the mixing layer thin and allowing low-energy ion bombardment to drive the continuous chemical etching [P4]. The etch directionality is maintained by the applied RF bias, which continuously clears the polymer from the trench bottom while allowing it to passivate the sidewalls, thereby preventing isotropic lateral etching [P3]. The selection of specific fluorocarbon gas chemistries, such as dynamically modulating the CF-to-CHF ratio, is dictated by the need for ultra-high material selectivity to the underlying SiCN etch stop layer [A1]. Because SiCN lacks internal oxygen to efficiently consume the fluorocarbon polymer, a thick, carbon-rich inhibiting layer naturally accumulates on its surface as the oxide etch reaches the interface, drastically suppressing F penetration and slowing the etch rate [P4]. Process parameter tuning must perfectly balance this polymerization mechanism: excessive polymerizing gas ratios can cause premature etch stop via inverse ARDE effects, while insufficient polymerization leads to a loss of selectivity and destructive etching of the underlying SiNx barrier [A1]. Furthermore, because this deep bond pad opening involves penetrating multiple accumulated layers, geometric shadowing reduces the neutral reactant flux reaching the bottom, a phenomenon fundamentally known as aspect-ratio-dependent etching (ARDE) [P2]. Process parameters such as operating pressure and ion energy must be carefully modulated to overcome these transport-limited delivery issues and maintain a consistent vertical etch rate [P2]. In 40nm BSI CMOS image sensors, the complex backend metallization and optical stacking require extremely precise deep dielectric etching without introducing severe plasma damage or thermo-mechanical stress [P1]. Maintaining absolute verticality and strict critical dimension (CD) control during the ILD 4-2 etch ensures that subsequent pad metallization and packaging connections are highly reliable and electrically isolated properly [A2]. The transition toward highly polymerized etch chemistries or atomic-layer-precision control is essential here to meet the stringent selectivity requirements dictated by the continuously shrinking thickness of intermediate SiCN barrier layers in advanced nodes [P4].