40nm BSI CMOS Image SensorPreview

lectric stack to expose the underlying metal pad [P3]. The etching is performed sequentially through alternating bulk oxide (ILD x-2) and thin SiCN etch-stop (ILD x-1) layers [P1]. Following the removal of the ILD 6 layers, the ILD 5-2 Oxide Etch specifically targets the bulk silicon dioxide of the 5th metal level, preparing the cavity to stop precisely on the underlying ILD 5-1 SiCN layer [P1]. Unlike superficial pad oxide etches that merely clear surface passivation, this step must maintain a highly anisotropic profile deep within an evolving high-aspect-ratio structure, making aspect-ratio scaling a primary process constraint [P2]. The oxide is typically etched using a fluorocarbon-based plasma, which relies on a delicate balance between chemical modification and physical ion bombardment [P1]. In the plasma environment, fluorocarbon gases (such as CHF3) deposit a sub-nanometer polymeric layer on the SiO2 surface, while Ar ions provide the directional kinetic energy required to remove this chemically modified layer [P1]. This synergistic mechanism ensures a highly anisotropic profile while the polymer protects the sidewalls from lateral etching [P1]. As the cavity deepens through multiple ILD layers, the transport of neutral reactant species becomes geometrically shadowed, leading to aspect-ratio-dependent etching (ARDE) where the etch rate decreases at the bottom of the structure [P2]. Therefore, the physical momentum transfer from ions becomes increasingly critical to clear reaction byproducts from the deep via [P3]. The choice of fluorocarbon/Ar chemistry over purely physical sputtering is driven by the need for high selectivity against the underlying SiCN etch stop layer and the photoresist mask [P1]. Process parameters must be carefully tuned; for instance, lower chamber pressures increase the ion mean free path and enhance the directionality of the ion bombardment, yielding vertical sidewalls with minimal undercut [P1]. Increasing the bias power enhances the physical component of the etch, which improves anisotropy but must be limited to prevent rapid degradation of the masking layers [P1]. If sidewall protection is insufficient due to a lack of polymerizing radicals, lateral etching can severely damage the dielectric material and compromise the structural integrity of the multi-layer cavity [A2]. At the 40nm node, the multi-layer dielectric stack experiences significant thermo-mechanical stress due to the varying coefficients of thermal expansion between the embedded metal routing and the oxide ILDs [A2]. Precise control of the etch profile during the ILD 5-2 step is necessary to avoid geometric stress concentrators on the sidewalls [P3]. Sharp morphological variations, analogous to the scallops seen in deep silicon etching, can amplify localized stresses and initiate dielectric cracking during subsequent high-pressure wire bonding or thermal packaging steps [P3].