40nm BSI CMOS Image SensorPreview

Bond Pad Cavity - Photo

246/ 417

ILD 6-2 Oxide Etch

ILD 6-1 SiCN Etch
245Bond Pad Cavity - Photo246ILD 6-2 Oxide Etch247ILD 6-1 SiCN Etch248ILD 5-2 Oxide Etch249ILD 5-1 SiCN Etch250ILD 4-2 Oxide Etch251ILD 4-1 SiCN Etch252ILD 3-2 Oxide Etch253Ashing & Strip/Clean254Ta-based Bottom Barrier deposition255Metal 7 Al Metal Deposition256Ta-based liner deposition257Pre Litho Cleaning258Metal 7 Bond Pad - Photo259Ta-Barrier etch260Al Metal Etch261Ta-Barrier etch262Ashing & Strip/Clean

Process Cross-Section

BONDPAD · B2 · ILD 6-2 Oxide Etchgate ox (SiO2, thermal)IO/HV gate ox (SiO2; relative thickness shown schematically; IO device not shown in this cross-section)TiSi (low-temp anneal)n- LDD (31P+, self-aligned)P-pinning (11B+)P+ VSS contact (11B+)FD node (31P+)VT adjust (11B+, periphery channel)SiO2 liner (SACVD)SiO2 (SACVD bulk fill)n+ S/D (31P+)n+ N-well contact (31P+)p+ surface passivation (10B+)Liner SiO2 (RTP thermal)P-well (pixel array, 11B+)P-well (periphery, 11B+)PD N-well (31P+)N-well (periphery, 31P+)SiP-well (implanted region)PRSiO2CESLCuTaPMD 5 (SiO2)PMD 4 (SiO2)MET0 (W)PMD 3 (SiO2 · CMP overburden)W (contact fill)PMD 2 (SiO2 · body segment)TiN (barrier)Ti (adhesion)Ti/TiN linerPMD 1 (SiO2 · bottom segment)CESL 2 (SiNO)SiNCESL 1 (SiN)PolySWS pad ox (SiO2, PECVD)

Step highlight

Material and parameter selections are heavily driven by the need for high etch selectivity between the target SiO2 and the underlying SiCN stop layer .

In depth

The ILD 6-2 Oxide Etch step is a critical back-end-of-line (BEOL) process designed to define the upper portion of the bond pad cavity for packag

ing or wafer-to-wafer integration . Following the "Bond Pad Cavity - Photo" step, this process anisotropically removes the thick uppermost silicon dioxide layer (ILD 6-2) and precisely stops on the underlying ILD 6-1 SiCN layer . This initiates a sequence of alternating dielectric and barrier etches (Oxide -> SiCN -> Oxide -> SiCN) necessary to expose the terminal metal interconnects without exposing sidewall metals . This step is distinctly different from front-end "Pad Oxide Etch" steps, which merely remove thin stress-relief oxides under nitride masks, and "Oxide Hard Mask Etch" steps, which define nanoscale interconnect trenches . Instead, this macro-scale etch must rapidly and uniformly remove a thick oxide film to accommodate complex bonding architectures, such as the high-density interconnects required in 3D-SOC and advanced image sensor applications . The physical mechanism of this step relies on the ion-chemical synergistic reactions characteristic of Reactive Ion Etching (RIE) . Fluorocarbon gases, such as CHF3 or CF4, are introduced into the plasma chamber and dissociated by RF power to generate highly reactive fluorine radicals and fluorocarbon ions . The fluorine radicals chemically attack the silicon dioxide matrix, breaking Si-O bonds to form volatile silicon fluoride byproducts that are evacuated from the chamber . Concurrently, the ionized species are accelerated across the plasma sheath by a direct-current bias, bombarding the wafer surface with directional kinetic energy . This physical bombardment clears passivation polymers from horizontal surfaces, ensuring the etch proceeds anisotropically to yield the steep sidewall profiles required for deep bond pad cavities . Material and parameter selections are heavily driven by the need for high etch selectivity between the target SiO2 and the underlying SiCN stop layer . SiCN is widely integrated in advanced hybrid bonding and BEOL stacks due to its high surface reactivity for bonding and its structural robustness as an etch stop . To maximize selectivity, the plasma chemistry must maintain a delicate balance; for instance, while adding oxygen can increase the overall oxide etch rate, it can simultaneously increase the etching of silicon-containing non-oxide layers, thereby severely degrading selectivity . Furthermore, RF power must be carefully optimized, as higher RF power raises the ion energy, which accelerates the etch rate but can induce severe physical damage to the etched surface and compromise the SiCN barrier . In the context of nanoscale Backside Illuminated (BSI) CMOS image sensors, the packaging layout often employs Bond Over Active (BOA) pad structures to minimize wasted die area by placing pads directly over active circuitry and multilayer interconnects . The mechanical reliability of these structures during wire bonding or packaging heavily depends on the progressive dispersion of transient mechanical loads through the multilayer metal and dielectric stack, which share similar elastic moduli . Consequently, the ILD 6-2 Oxide Etch must avoid creating structural defects, severe undercuts, or micro-cracks in the dielectric, as such geometric flaws can act as stress concentration points that ultimately cause mechanical failure at the contact-silicon interface during packaging stresses .

Risks & Challenges

  • [High] Etch Stop Punchthrough: Excessive RF power or improper gas chemistry can raise the kinetic energy of bombarding ions, leading to physical damage and unintended etching of the underlying SiCN layer .
  • [Medium] Excessive Polymer Deposition: In fluorocarbon-based RIE, an imbalance toward high polymerizing gas flow or insufficient ion energy can cause thick fluorocarbon polymers to accumulate at the bottom of the pad cavity, blocking further etching and leaving unetched oxide residues .
  • [Low] Pad Structure Mechanical Weakening: Isotropic etching components or severe sidewall bowing can alter the geometric integrity of the thick dielectric stack, impairing its ability to safely dissipate transient mechanical loads during subsequent wire bonding or hybrid bonding steps .

Sign in to continue through all 417 steps

Sign up with emailLog in

Related steps

  • Bond Pad Cavity - Photo
  • ILD 6-1 SiCN Etch
  • ILD 5-2 Oxide Etch
  • ILD 5-1 SiCN Etch
  • ILD 4-2 Oxide Etch
  • ILD 4-1 SiCN Etch