40nm BSI CMOS Image SensorPreview

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Upper Vertical Grid Barrier Deposition

Upper Vertical Grid Deposition
346Optical Pad 3 Deposition347Optical Pad 3 CMP348Post CMP Cleaning349Pre Litho Cleaning350Mid Vertical Grid Trench - Photo351Optical Pad 3 Etch352Lower OCL Coating Etch353Lower OCL Etch354Optical Pad 2 Etch355Ashing & Strip/Clean356Mid Vertical Grid Deposition357W CMP358Post CMP Cleaning359Upper Vertical Grid Barrier Deposition360Upper Vertical Grid Deposition361Pre Litho Cleaning362Upper Vertical Grid - Photo363W Etch364TiN Etch365Ashing & Strip/Clean366Upper Grid Seal Layer Deposition367Pre Litho Cleaning

Process Cross-Section

ISP WaferCIS Wafer · BacksideLS_GRID · L35 · Upper Vertical Grid Barrier DepositionTaOAlOP+ implanted regionSiCESLSiO2CuTaAlOptical Pad 3Lower OCLSiNSiONOptical Pad 1Grid SealWTiNBPMD

Step highlight

TiN barrier deposition prevents interdiffusion between mid-grid and upper-grid materials by forming a stable interface .

In depth

Following Mid Vertical Grid Deposition and W CMP, the wafer presents a planarized surface with exposed mid-grid metal and dielectric regions (Engineering Practice). The Upper

Vertical Grid Barrier Deposition step prepares the interface for the subsequent Upper Vertical Grid Deposition by providing an essential adhesion and diffusion-blocking layer . Unlike the Ta-based Bottom Barrier (step #254) which often lines high-aspect-ratio deep trench isolation directly contacting the silicon substrate, this upper barrier sits higher in the metallization stack to interface the mid-grid and upper-grid materials . The barrier ensures structural integrity and prevents interdiffusion between dissimilar metals, which is critical for maintaining long-term reliability in highly integrated structures . The deposition of the barrier, typically a titanium nitride (TiN) film, relies heavily on surface-limited reactions when atomic layer deposition (ALD) is utilized . During the initial growth phase on exposed dielectric surfaces, the TiN film follows a Stranski–Krastanov growth mode, transitioning from a two-dimensional layered growth to three-dimensional island formation due to the competition between interface energy and strain energy . To form a continuous, sub-nanometer ultra-thin barrier, low-pressure conditions are favored to enhance the surface mobility of adsorbates, promoting rapid lateral island coalescence . If the process employs low-temperature plasma-enhanced chemical vapor deposition (PECVD) to respect the thermal budget, plasma-activated nitrogen species directly cleave precursor bonds, driving the reaction via non-thermal plasma chemistry rather than thermal equilibrium decomposition . TiN is selected as the barrier material because of its excellent chemical inertness, high thermal stability, and inherently low electrical resistivity . To achieve the required step coverage and conformality over any remaining topography, ALD is often preferred over conventional physical vapor deposition (PVD) methods . Furthermore, introducing chemical modulators like tertiary alkyl halides during thermal ALD can selectively modulate the surface chemical reactivity . These additives act as transient growth inhibitors that preferentially adsorb on highly reactive surface sites, making the reaction more diffusion-controlled and thereby improving conformality without introducing carbon impurities . Alternatively, if reactive sputtering is used, controlling the reactive gas ratios can yield a (100)-preferred crystal orientation, which forms a dense, columnar fibrous grain structure that disrupts fast diffusion paths along grain boundaries . In a 40nm BSI CMOS Image Sensor, pixel dimensions are aggressively scaled, demanding extremely thin yet continuous grid structures to maximize the optical fill factor (Engineering Practice). As device dimensions shrink toward fundamental thermodynamic scaling limits, the physical constraints on barrier thickness become increasingly severe . The barrier must be thick enough to prevent interdiffusion but thin enough not to consume the spatial volume required for the highly reflective or absorptive upper grid metal . This structural requirement mandates precise monitoring of the initial nucleation phase to ensure the film reaches its continuity closure point at the absolute minimum thickness .

Risks & Challenges

  • [High] Discontinuous Film Nucleation: If the barrier material fails to coalesce from three-dimensional islands into a continuous layer at the target thickness, it leaves unpassivated pathways for metal diffusion . This failure mode is driven by insufficient adsorbate surface mobility, often caused by suboptimal deposition temperature or process pressure .
  • [Medium] High Film Resistivity from Impurities: Incomplete ligand exchange during the ALD or PECVD process can leave residual chlorine or carbon impurities embedded within the deposited film . These impurities act as scattering centers, leading to a sharp increase in resistivity that degrades the performance of the grid structure .
  • [Medium] Poor Conformality and Step Coverage: If the surface reaction rate is excessively fast compared to reactant diffusion, reactant depletion occurs near the upper edges of the local topography . This kinetic imbalance leads to thicker deposition at the top and reduced coverage at the bottom, potentially causing voids during the subsequent Upper Vertical Grid Deposition (Engineering Practice).
  • [Low] Unstable Interface and Recrystallization: Depositing the barrier at excessively low temperatures without proper orientation control can yield a thermodynamically metastable, less-dense film . Subsequent thermal cycling can induce recrystallization, which alters the grain boundary structure and creates fast diffusion paths that compromise the barrier's long-term integrity .

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Related steps

  • LS/Aperture Grid Barrier Deposition
  • LS/Aperture Grid Deposition
  • Oxide Grid Seal Layer Deposition
  • Pre Litho Cleaning
  • Light Shield/Aperture Grid - Photo
  • Oxide Grid Seal Layer Etch