Upper Vertical Grid Barrier Deposition - 40nm

TiN barrier deposition prevents interdiffusion between mid-grid and upper-grid materials by forming a stable interface [A2].

Following Mid Vertical Grid Deposition and W CMP, the wafer presents a planarized surface with exposed mid-grid metal and dielectric regions (Engineering Practice). The Uppe…

TiN barrier deposition prevents interdiffusion between mid-grid and upper-grid materials by forming a stable interface [A2].

Following Mid Vertical Grid Deposition and W CMP, the wafer presents a planarized surface with exposed mid-grid metal and dielectric regions (Engineering Practice). The Uppe…

40nm BSI CMOS Image SensorFree after sign-in

Process Cross-Section

Step highlight

In depth

40nm BSI CMOS Image SensorFree after sign-in

Process Cross-Section

Step highlight

In depth